In this study there are thus 3 possible sources of ADC gate times whoseeffectiveness can be looked at. First is the the PST derived trigger time.Second is a Multiplicity trigger time when the CFD fraction is set to 33%(MULT3). The last is a Multiplicity trigger time when the CFD fraction is setto 66% (MULT6). Igenerated a large number of all these triggers using a 700 GeV proton shower and looked at the distribution of timing differences between the PST and MULT3 triggers and the PST and the MULT6 triggers. These are shown in Figures 3a and 3b . The constant offset is ignorable and the second set of very early triggersfor the MULT3 can be clearly seen in the MULT3 plot. Raising the MULTFRACto 66% clearly corrects this error. The interpretation of the differences in widths of the two distributions is subtle. Naively I would have expected the MULT6-PST distribution to be narrower to indicate that the MULT6 scheme is abetter way to determine the trigger time. Well it actually is. What happens is that the MULT3 trigger behaves more like the PST trigger. That is, it makesimular errors as the PST so that the differences between the two are small. The MULT6 scheme does a better job of correcting for slewing and so itsdifference from the PST is wider.
To determine the effectiveness of these different ADC gate generationschemes I made a series of plots using the trigger times to determine where toplace the ADC gate on the Pixel output waveform. I superimpose a series ofthese plots from a large number of triggers. Figure 4 andFigure 5 show various plots for all pulse heights and for large pulse heights for the3 triggers. Clearly the 20ns gate width isadequate, probably even if the PST trigger is used for timing. Itshould be noted here that the actual position of the ADC gate relative tothe trigger time in all trigger schemes was determined by eye. In fact, itappears that I could have moved the MULT6 ADC gate 1 ns earlier to better contain the shower pulses.
To see what amount of the signal pulses were not contained by the gate using thedifferent triggering schemes, the amount of pulse in the 10 ns precedingthe gate (1/2 the gate width) and in the 10 ns after the gate was determinedand summed. If the gate containes the pulsescompletely, the sum of these 2 areas, which covers a total of 20 ns as does thegate, should be the pedestal distribution.(see Figures 6a,6b and 6c ).Early in the pulse generation scheme I determined an average pedestal bygenerating many noise waveforms and finding the average value in arandomly placed 20 ns gate. This constant value , the pedestal, wassubtracted from all the pulses shown here. If the shower pulses are totally contained by the ADC gate then Figures 6a,6b and 6c should have a mean of 0 and a width equal to the expected pedestal width (see above). I can also lookat this distribution for large pulses (see Figures 7a,7b and 7c ). These plots indicate thatthe use of the MULT6 trigger is somewhat better then the MULT3 schemes andperhaps just slightly better then the PST timing forpositioning the ADC gate and that the 20 ns width of the ADC gate is adequatein containing even the biggest pulses that were modeled.