[16:29:12.502]     INFO: *** Welcome to pxar ***
[16:29:12.502]     INFO: *** Today: 2016/09/07
[16:29:12.526]     INFO: *** Version: v1.9.0-818-g96727
[16:29:12.526]     INFO: readRocDacs: data/mp315/dacParameters35_C0.dat .. data/mp315/dacParameters35_C15.dat
[16:29:12.527]     INFO: readTbmDacs: data/mp315/tbmParameters_C0a.dat .. data/mp315/tbmParameters_C0b.dat
[16:29:12.527]     INFO: readMaskFile: data/mp315/defaultMaskFile.dat
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 5
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 6
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 7
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 8
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 9
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 10
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 11
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 12
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 13
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 50 15
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 3
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 4
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 5
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 6
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 7
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 8
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 9
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 10
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 11
[16:29:12.527]     INFO: MASKED Roc 0 col/row: 51 12
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 13
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 14
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 15
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 16
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 17
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 18
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 19
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 20
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 21
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 22
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 23
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 24
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 25
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 26
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 27
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 28
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 29
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 30
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 31
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 32
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 33
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 34
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 35
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 36
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 37
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 38
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 39
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 40
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 41
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 42
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 43
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 44
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 45
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 46
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 47
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 48
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 49
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 50
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 51
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 56
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 57
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 58
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 60
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 61
[16:29:12.528]     INFO: MASKED Roc 0 col/row: 51 62
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 29 10
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 29 11
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 29 12
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 29 13
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 29 14
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 9
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 10
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 11
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 12
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 13
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 14
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 30 15
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 8
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 9
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 10
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 11
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 12
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 13
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 14
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 15
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 31 16
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 9
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 10
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 11
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 12
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 13
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 14
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 15
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 32 16
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 10
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 11
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 12
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 13
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 14
[16:29:12.528]     INFO: MASKED Roc 1 col/row: 33 15
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 33 26
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 33 27
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 9
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 10
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 11
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 12
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 13
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 26
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 27
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 34 28
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 9
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 10
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 11
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 12
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 13
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 14
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 15
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 16
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 25
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 26
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 27
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 28
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 29
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 37
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 35 38
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 36 27
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 36 38
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 36 40
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 36 42
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 41
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 42
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 43
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 48
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 49
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 53
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 37 54
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 48
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 49
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 50
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 51
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 52
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 53
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 38 54
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 51
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 52
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 53
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 54
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 55
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 56
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 57
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 39 58
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 40 53
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 40 57
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 40 58
[16:29:12.529]     INFO: MASKED Roc 1 col/row: 40 59
[16:29:12.529]     INFO: readTrimFile: data/mp315/trimParameters35_C0.dat .. data/mp315/trimParameters35_C15.dat
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 5
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 6
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 7
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 8
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 9
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 10
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 11
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 12
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 13
[16:29:12.530]     INFO:   masking Roc 0 col/row: 50 15
[16:29:12.530]     INFO:   masking Roc 0 col/row: 51 3
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 4
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 5
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 6
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 7
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 8
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 9
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 10
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 11
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 12
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 13
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 14
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 15
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 16
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 17
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 18
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 19
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 20
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 21
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 22
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 23
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 24
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 25
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 26
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 27
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 28
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 29
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 30
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 31
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 32
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 33
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 34
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 35
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 36
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 37
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 38
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 39
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 40
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 41
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 42
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 43
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 44
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 45
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 46
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 47
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 48
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 49
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 50
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 51
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 56
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 57
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 58
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 60
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 61
[16:29:12.531]     INFO:   masking Roc 0 col/row: 51 62
[16:29:12.541]     INFO:   masking Roc 1 col/row: 29 10
[16:29:12.541]     INFO:   masking Roc 1 col/row: 29 11
[16:29:12.541]     INFO:   masking Roc 1 col/row: 29 12
[16:29:12.541]     INFO:   masking Roc 1 col/row: 29 13
[16:29:12.541]     INFO:   masking Roc 1 col/row: 29 14
[16:29:12.541]     INFO:   masking Roc 1 col/row: 30 9
[16:29:12.541]     INFO:   masking Roc 1 col/row: 30 10
[16:29:12.541]     INFO:   masking Roc 1 col/row: 30 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 30 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 30 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 30 14
[16:29:12.542]     INFO:   masking Roc 1 col/row: 30 15
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 8
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 9
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 10
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 14
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 15
[16:29:12.542]     INFO:   masking Roc 1 col/row: 31 16
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 9
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 10
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 14
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 15
[16:29:12.542]     INFO:   masking Roc 1 col/row: 32 16
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 10
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 14
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 15
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 26
[16:29:12.542]     INFO:   masking Roc 1 col/row: 33 27
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 9
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 10
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 26
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 27
[16:29:12.542]     INFO:   masking Roc 1 col/row: 34 28
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 9
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 10
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 11
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 12
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 13
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 14
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 15
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 16
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 25
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 26
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 27
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 28
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 29
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 37
[16:29:12.542]     INFO:   masking Roc 1 col/row: 35 38
[16:29:12.542]     INFO:   masking Roc 1 col/row: 36 27
[16:29:12.542]     INFO:   masking Roc 1 col/row: 36 38
[16:29:12.542]     INFO:   masking Roc 1 col/row: 36 40
[16:29:12.542]     INFO:   masking Roc 1 col/row: 36 42
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 41
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 42
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 43
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 48
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 49
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 53
[16:29:12.542]     INFO:   masking Roc 1 col/row: 37 54
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 48
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 49
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 50
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 51
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 52
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 53
[16:29:12.543]     INFO:   masking Roc 1 col/row: 38 54
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 51
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 52
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 53
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 54
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 55
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 56
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 57
[16:29:12.543]     INFO:   masking Roc 1 col/row: 39 58
[16:29:12.543]     INFO:   masking Roc 1 col/row: 40 53
[16:29:12.543]     INFO:   masking Roc 1 col/row: 40 57
[16:29:12.543]     INFO:   masking Roc 1 col/row: 40 58
[16:29:12.543]     INFO:   masking Roc 1 col/row: 40 59
[16:29:12.683]     INFO:         clk: 4
[16:29:12.683]     INFO:         ctr: 4
[16:29:12.683]     INFO:         sda: 19
[16:29:12.683]     INFO:         tin: 9
[16:29:12.683]     INFO:         level: 15
[16:29:12.683]     INFO:         triggerdelay: 0
[16:29:12.683]    QUIET: Instanciating API for pxar v1.9.0+818~g9672706
[16:29:12.683]     INFO: Log level: DEBUG
[16:29:12.734]    QUIET: Connection to board DTB_WRPRHI opened.
[16:29:12.737]     INFO: DTB startup information
--- DTB info------------------------------------------
Board id:    58
HW version:  DTB1.2
FW version:  4.2
SW version:  4.5
USB id:      DTB_WRPRHI
MAC address: 40D85511803A
Hostname:    pixelDTB058
Comment:     
------------------------------------------------------
[16:29:12.740]     INFO: RPC call hashes of host and DTB match: 398089610
[16:29:14.344]     INFO: DUT info: 
[16:29:14.344]     INFO: The DUT currently contains the following objects:
[16:29:14.344]     INFO:  2 TBM Cores tbm08c (2 ON)
[16:29:14.344]     INFO: 	TBM Core alpha (0): 7 registers set
[16:29:14.344]     INFO: 	TBM Core beta  (1): 7 registers set
[16:29:14.344]     INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[16:29:14.344]     INFO: 	ROC 0: 19 DACs set, Pixels: 65 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 1: 19 DACs set, Pixels: 90 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.344]     INFO: 	ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.345]     INFO: 	ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.345]     INFO: 	ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB<-
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB2<-
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 222
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   plwidth: 35
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB3<-
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB4<-
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   savecaldelscan: checkbox(0)
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 100
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   cals: 1
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   caldello: 80
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelhi: 200
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelstep: 10
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomplo: 70
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomphi: 130
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompstep: 5
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   noisypixels: 10
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 255
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L107>   cut: 0.5
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Cmd<-
[16:29:14.345]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DAQ<-
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   trgnumber: 5
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqtrg: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   daqseconds: 5
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqseconds: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacDacScan<-
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1: caldel
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1lo: 0
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1hi: 255
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2: vthrcomp
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2lo: 0
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2hi: 255
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacScan<-
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox(1)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   allpixels: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   unmasked: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: vcal
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 255
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->GainPedestal<-
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   showfits: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   extended: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dumphists: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   vcalstep: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   measure: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   fit: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   save: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->HighRate<-
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixels: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixelthr: 200
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   runsecondshotpixels: 10
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   savetrimbits: checkbox(1)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   maskuntrimmable: checkbox(1)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelscan: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   xpixelalive: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   xnoisemaps: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 100
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: 20
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaq: button
[16:29:14.346]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 20
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 2
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   triggerdelay: 20
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->IV<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   port: /dev/FIXME
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestart: 0
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestop: 600
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestep: 5
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   delay: 1
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   compliance(ua): 100
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PhOptimization<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   safetymarginlow: 20
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   saturationvcal: 100
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   quantilesaturation: 0.98
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PixelAlive<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   alivetest: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   masktest: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   addressdecodingtest: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Pretest<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   programroc: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 100
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   settimings: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   findtiming: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   findworkingpixel: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   setvthrcompcaldel: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 250
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   deltavthrcomp: 50
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   fraccaldel: 0.5
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   savedacs: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Readback<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   calibratevd: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateva: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateia: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   readbackvbg: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   getcalibratedvbg: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalvd: checkbox(1)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalva: checkbox(0)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Scurves<-
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   adjustvcal: checkbox(0)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpoutputfile: checkbox(0)
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: Vcal
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:29:14.347]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 200
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: -1
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig/step: -1
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   scurves: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Timing<-
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   targetclk: 4
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   clocksdascan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   notokenpass: checkbox(0)
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   phasescan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   levelscan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   tbmphasescan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   rocdelayscan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   timingtest: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   saveparameters: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Trim<-
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   trim: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 8
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 35
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   trimbits: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Xray<-
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   source: Ag
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   phrun: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 100
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   ratescan: button
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmin: 10
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmax: 80
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   stepseconds: 5
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:29:14.348]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L81> PixSetup init start; getCurrentRSS() = 34816000
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L87> fPixTestParameters = 0x1c2e0b0
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L88>  fConfigParameters = 0x19d0370
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L89>        fPxarMemory = 0x7fa67dd94010
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L90>         fPxarMemHi = 0x7fa683fff510
[16:29:14.350]    DEBUG: <PixSetup.cc/init:L106> PixSetup init done;  getCurrentRSS() = 34824192 fPxarMemory = 0x7fa67dd94010
[16:29:14.352]    DEBUG: <pXar.cc/main:L223> Initial Analog Current: 394.7mA
[16:29:14.353]    DEBUG: <pXar.cc/main:L224> Initial Digital Current: 471.1mA
[16:29:14.353]    DEBUG: <pXar.cc/main:L225> Initial Module Temperature: -0.2 C
[16:29:14.874]    DEBUG: <PixGui.cc/hvOn:L460> HV set On: 0x201d4a0
[16:29:14.938]    DEBUG: <PixTestFactory.cc/PixTestFactory:L53> PixTestFactory::PixTestFactory()
[16:29:14.938]    DEBUG: <PixTestBBMap.cc/init:L79> PixTestBBMap::init()
[16:29:14.938]    DEBUG: <PixTestBBMap.cc/PixTestBBMap:L27> PixTestBBMap ctor(PixSetup &a, string, TGTab *)
[16:29:14.944]    DEBUG: <PixTestBB2Map.cc/setParameter:L58> setting fTargetIa    = 24 mA/ROC
[16:29:14.944]    DEBUG: <PixTestBB2Map.cc/init:L97> PixTestBB2Map::init()
[16:29:14.944]    DEBUG: <PixTestBB2Map.cc/PixTestBB2Map:L29> PixTestBB2Map ctor(PixSetup &a, string, TGTab *)
[16:29:14.954]    DEBUG: <PixTestBB3Map.cc/init:L81> PixTestBB3Map::init()
[16:29:14.954]    DEBUG: <PixTestBB3Map.cc/PixTestBB3Map:L29> PixTestBB3Map ctor(PixSetup &a, string, TGTab *)
[16:29:14.978]    DEBUG: <PixTestBB4Map.cc/init:L93> PixTestBB4Map::init()
[16:29:14.978]    DEBUG: <PixTestBB4Map.cc/PixTestBB4Map:L26> PixTestMapeff ctor(PixSetup &a, string, TGTab *)
[16:29:14.987]     INFO: PixTestCmd::init()
[16:29:14.992]    DEBUG: <PixTestDaq.cc/init:L44> PixTestDaq::init()
[16:29:14.992]    DEBUG: <PixTestDaq.cc/PixTestDaq:L22> PixTestDaq ctor(PixSetup &a, string, TGTab *)
[16:29:14.992]     INFO: readGainPedestalParameters data/mp315/phCalibrationFitErr35_C0.dat .. data/mp315/phCalibrationFitErr35_C15.dat
[16:29:15.244]    DEBUG: <PixTestDacDacScan.cc/init:L103> PixTestDacDacScan::init()
[16:29:15.244]    DEBUG: <PixTestDacDacScan.cc/PixTestDacDacScan:L22> PixTestDacDacScan ctor(PixSetup &a, string, TGTab *)
[16:29:15.257]    DEBUG: <PixTestGainPedestal.cc/setParameter:L83> PixTestGainPedestal::PixTest() fVcalStep = 10
[16:29:15.263]    DEBUG: <PixTestHighRate.cc/setParameter:L68>   setting fParTriggerFrequency -> 20
[16:29:15.263]    DEBUG: <PixTestHighRate.cc/init:L211> PixTestHighRate::init()
[16:29:15.263]    DEBUG: <PixTestHighRate.cc/PixTestHighRate:L31> PixTestHighRate ctor(PixSetup &a, string, TGTab *)
[16:29:15.286]    DEBUG: <PixTest.cc/setTestParameter:L637>  setting  ntrig to new value 10
[16:29:15.286]    DEBUG: <PixTestPhOptimization.cc/setParameter:L37>   setting fParNtrig  ->10<- from sval = 10
[16:29:15.286]    DEBUG: <PixTestPhOptimization.cc/setParameter:L42>   setting fSafetyMarginLow  ->20<- from sval = 20
[16:29:15.286]    DEBUG: <PixTestPhOptimization.cc/setParameter:L48>   setting fVcalMax  ->100<- from sval = 100
[16:29:15.286]    DEBUG: <PixTestPhOptimization.cc/setParameter:L53>   setting fQuantMax  ->0.98<- from sval = 0.98
[16:29:15.296]    DEBUG: <PixTestAlive.cc/init:L83> PixTestAlive::init()
[16:29:15.297]    DEBUG: <PixTestAlive.cc/PixTestAlive:L21> PixTestAlive ctor(PixSetup &a, string, TGTab *)
[16:29:15.318]    DEBUG: <PixTestReadback.cc/setParameter:L172> fCalwVd set to 1
[16:29:15.318]    DEBUG: <PixTestReadback.cc/init:L95> PixTestReadback::init()
[16:29:15.319]    DEBUG: <PixTestReadback.cc/PixTestReadback:L22> PixTestReadback ctor(PixSetup &a, string, TGTab *)
[16:29:15.319]     INFO: readReadbackCal: data/mp315/readbackCal_C0.dat .. data/mp315/readbackCal_C15.dat
[16:29:15.328]    DEBUG: <PixTestScurves.cc/setParameter:L93> set fOutputFilename = 
[16:29:15.336]    DEBUG: <PixTestTiming.cc/setParameter:L59> PixTestTiming::PixTest() targetclk = 4
[16:29:15.336]    DEBUG: <PixTestTiming.cc/setParameter:L63> PixTestTiming::PixTest() ntrig = 10
[16:29:15.336]    DEBUG: <PixTestTiming.cc/setParameter:L47> fNoTokenPass: 0
[16:29:15.336]    DEBUG: <PixTestTiming.cc/init:L73> PixTestTiming::init()
[16:29:15.358]    DEBUG: <PixTestXray.cc/init:L135> PixTestXray::init()
[16:29:15.358]    DEBUG: <PixTestXray.cc/PixTestXray:L28> PixTestXray ctor(PixSetup &a, string, TGTab *)
[16:29:29.738]     INFO: ######################################################################
[16:29:29.738]     INFO: PixTestXray::doTest()
[16:29:29.738]     INFO: ######################################################################
[16:29:29.738]     INFO:    ----------------------------------------------------------------------
[16:29:29.738]     INFO:    PixTestXray::doPhRun() fParRunSeconds = 100
[16:29:29.738]     INFO:    ----------------------------------------------------------------------
[16:29:29.741]     INFO: ROC 0 masking hot pixel 50/5
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[16:29:29.743]     INFO: ROC 1 masking hot pixel 29/10
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[16:29:29.743]     INFO: ROC 1 masking hot pixel 33/10
[16:29:29.743]     INFO: ROC 1 masking hot pixel 33/11
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 33/15
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 33/27
[16:29:29.744]     INFO: ROC 1 masking hot pixel 34/9
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 34/11
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 34/27
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/9
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/11
[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/12
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/14
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[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/27
[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/28
[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/29
[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/37
[16:29:29.744]     INFO: ROC 1 masking hot pixel 35/38
[16:29:29.744]     INFO: ROC 1 masking hot pixel 36/27
[16:29:29.744]     INFO: ROC 1 masking hot pixel 36/38
[16:29:29.744]     INFO: ROC 1 masking hot pixel 36/40
[16:29:29.744]     INFO: ROC 1 masking hot pixel 36/42
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/41
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/42
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/43
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/48
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/49
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/53
[16:29:29.744]     INFO: ROC 1 masking hot pixel 37/54
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/48
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/49
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/50
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/51
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/52
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/53
[16:29:29.744]     INFO: ROC 1 masking hot pixel 38/54
[16:29:29.744]     INFO: ROC 1 masking hot pixel 39/51
[16:29:29.744]     INFO: ROC 1 masking hot pixel 39/52
[16:29:29.744]     INFO: ROC 1 masking hot pixel 39/53
[16:29:29.744]     INFO: ROC 1 masking hot pixel 39/54
[16:29:29.745]     INFO: ROC 1 masking hot pixel 39/55
[16:29:29.745]     INFO: ROC 1 masking hot pixel 39/56
[16:29:29.745]     INFO: ROC 1 masking hot pixel 39/57
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[16:29:29.745]     INFO: ROC 1 masking hot pixel 40/53
[16:29:29.745]     INFO: ROC 1 masking hot pixel 40/57
[16:29:29.745]     INFO: ROC 1 masking hot pixel 40/58
[16:29:29.745]     INFO: ROC 1 masking hot pixel 40/59
[16:29:29.745]     INFO: ROC 0 masking pixel 50/5
[16:29:29.745]     INFO: ROC 0 masking pixel 50/6
[16:29:29.745]     INFO: ROC 0 masking pixel 50/7
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[16:29:29.745]     INFO: ROC 0 masking pixel 50/11
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[16:29:29.745]     INFO: ROC 0 masking pixel 50/15
[16:29:29.745]     INFO: ROC 0 masking pixel 51/3
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[16:29:29.745]     INFO: ROC 0 masking pixel 51/6
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[16:29:29.745]     INFO: ROC 0 masking pixel 51/11
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[16:29:29.745]     INFO: ROC 0 masking pixel 51/18
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[16:29:29.745]     INFO: ROC 0 masking pixel 51/22
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[16:29:29.746]     INFO: ROC 0 masking pixel 51/30
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[16:29:29.746]     INFO: ROC 0 masking pixel 51/39
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[16:29:29.746]     INFO: ROC 1 masking pixel 29/10
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[16:29:29.748]     INFO: ROC 1 masking pixel 39/51
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[16:29:29.748]     INFO: ROC 1 masking pixel 40/53
[16:29:29.748]     INFO: ROC 1 masking pixel 40/57
[16:29:29.748]     INFO: ROC 1 masking pixel 40/58
[16:29:29.748]     INFO: ROC 1 masking pixel 40/59
[16:29:30.718]     INFO: PixTestXray::doPhRun start TriggerLoop with trigger frequency 100 kHz, period 405 and duration 100 seconds,  fEventsMax = 10000000
[16:29:43.974]     INFO: run duration 13 seconds, buffer almost full (81%), pausing triggers.
[16:29:43.978]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:30:12.000]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306150 events.
[16:30:17.145]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306150, pixels seen in all events: 4571920
[16:30:17.250]     INFO: Resuming triggers.
[16:30:30.515]     INFO: run duration 26 seconds, buffer almost full (81%), pausing triggers.
[16:30:30.547]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:30:58.200]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306861 events.
[16:31:03.330]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306861, pixels seen in all events: 4563052
[16:31:03.484]     INFO: Resuming triggers.
[16:31:16.752]     INFO: run duration 39 seconds, buffer almost full (81%), pausing triggers.
[16:31:16.782]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:31:44.380]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1307082 events.
[16:31:49.444]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1307082, pixels seen in all events: 4559705
[16:31:49.661]     INFO: Resuming triggers.
[16:32:02.924]     INFO: run duration 52 seconds, buffer almost full (81%), pausing triggers.
[16:32:02.958]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:32:30.565]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306676 events.
[16:32:35.679]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306676, pixels seen in all events: 4564768
[16:32:35.902]     INFO: Resuming triggers.
[16:32:49.163]     INFO: run duration 66 seconds, buffer almost full (81%), pausing triggers.
[16:32:49.204]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:33:16.888]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306462 events.
[16:33:22.010]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306462, pixels seen in all events: 4567820
[16:33:22.117]     INFO: Resuming triggers.
[16:33:35.384]     INFO: run duration 79 seconds, buffer almost full (81%), pausing triggers.
[16:33:35.423]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:34:02.989]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306986 events.
[16:34:08.110]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306986, pixels seen in all events: 4561697
[16:34:08.218]     INFO: Resuming triggers.
[16:34:21.484]     INFO: run duration 92 seconds, buffer almost full (81%), pausing triggers.
[16:34:21.522]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:34:49.265]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 1306924 events.
[16:34:54.403]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 1306924, pixels seen in all events: 4561903
[16:34:54.575]     INFO: Resuming triggers.
[16:35:01.858]     INFO: data taking finished, elapsed time: 100 seconds.
[16:35:02.055]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:35:17.243]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 717463 events.
[16:35:20.013]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 717463, pixels seen in all events: 2506684
[16:35:20.165]     INFO: PixTest::       pg_setup set to default.
[16:35:20.212]     INFO: PixTestXray::doPhRun() done
[16:35:20.212]     INFO: PixTestXray::doTest() done 
[16:36:19.250]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:36:19.250]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = qMap_Ag_C11_V0 -> qMap_Ag_mod
[16:36:44.746]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:36:44.746]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = hMap_Ag_C4_V0 -> hMap_Ag_mod
[16:36:46.834]    DEBUG: <PixGui.cc/handleButtons:L396> PixGui::exit called
[16:36:46.835]    DEBUG: <PixGui.cc/CloseWindow:L335> Final Analog Current: 399.5mA
[16:36:46.836]    DEBUG: <PixGui.cc/CloseWindow:L336> Final Digital Current: 471.1mA
[16:36:46.836]    DEBUG: <PixGui.cc/CloseWindow:L337> Final Module Temperature: -0.1 C
[16:36:46.836]    DEBUG: <PixTestBBMap.cc/~PixTestBBMap:L97> PixTestBBMap dtor
[16:36:46.836]    DEBUG: <PixTestBB2Map.cc/~PixTestBB2Map:L115> PixTestBB2Map dtor
[16:36:46.836]    DEBUG: <PixTestBB3Map.cc/~PixTestBB3Map:L99> PixTestBB3Map dtor
[16:36:46.836]    DEBUG: <PixTestBB4Map.cc/~PixTestBB4Map:L118> PixTestBB4Map dtor
[16:36:46.836]    DEBUG: <PixTestCmd.cc/~PixTestCmd:L78> PixTestCmd dtor
[16:36:46.836]    DEBUG: <PixTestDaq.cc/~PixTestDaq:L37> PixTestDaq dtor
[16:36:46.836]    DEBUG: <PixTestDacDacScan.cc/~PixTestDacDacScan:L136> PixTestDacDacScan dtor
[16:36:46.836]    DEBUG: <PixTestDacScan.cc/~PixTestDacScan:L129> PixTestDacScan dtor
[16:36:46.836]    DEBUG: <PixTestGainPedestal.cc/~PixTestGainPedestal:L125> PixTestGainPedestal dtor
[16:36:46.836]    DEBUG: <PixTestHighRate.cc/~PixTestHighRate:L258> PixTestHighRate dtor
[16:36:46.836]    DEBUG: <PixTestIV.cc/~PixTestIV:L96> PixTestIV dtor
[16:36:46.836]    DEBUG: <PixTestAlive.cc/~PixTestAlive:L115> PixTestAlive dtor
[16:36:46.836]    DEBUG: <PixTestPretest.cc/~PixTestPretest:L136> PixTestPretest dtor
[16:36:46.837]    DEBUG: <PixTestReadback.cc/~PixTestReadback:L89> PixTestReadback dtor, saving tree ... 
[16:36:46.837]    DEBUG: <PixTestScurves.cc/~PixTestScurves:L142> PixTestScurves dtor
[16:36:46.837]    DEBUG: <PixTestTiming.cc/~PixTestTiming:L96> PixTestTiming dtor
[16:36:46.837]    DEBUG: <PixTestTrim.cc/~PixTestTrim:L103> PixTestTrim dtor
[16:36:46.837]    DEBUG: <PixTestXray.cc/~PixTestXray:L218> PixTestXray dtor
[16:36:47.152]    QUIET: Connection to board 58 closed.
[16:36:47.232]    DEBUG: <PixMonitor.cc/dumpSummaries:L39> PixMonitor::dumpSummaries
									 
									
									
															
						
							
						
						[16:36:52.813]     INFO: *** Welcome to pxar ***
[16:36:52.813]     INFO: *** Today: 2016/09/07
[16:36:52.837]     INFO: *** Version: v1.9.0-818-g96727
[16:36:52.837]     INFO: readRocDacs: data/mp315/dacParameters35_C0.dat .. data/mp315/dacParameters35_C15.dat
[16:36:52.838]     INFO: readTbmDacs: data/mp315/tbmParameters_C0a.dat .. data/mp315/tbmParameters_C0b.dat
[16:36:52.838]     INFO: readMaskFile: data/mp315/defaultMaskFile.dat
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 5
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 6
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 7
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 8
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 9
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 10
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 11
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 12
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 13
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 50 15
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 3
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 4
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 5
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 6
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 7
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 8
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 9
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 10
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 11
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 12
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 13
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 14
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 15
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 16
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 17
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 18
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 19
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 20
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 21
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 22
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 23
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 24
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 25
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 26
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 27
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 28
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 29
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 30
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 31
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 32
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 33
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 34
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 35
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 36
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 37
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 38
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 39
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 40
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 41
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 42
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 43
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 44
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 45
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 46
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 47
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 48
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 49
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 50
[16:36:52.839]     INFO: MASKED Roc 0 col/row: 51 51
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 56
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 57
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 58
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 60
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 61
[16:36:52.840]     INFO: MASKED Roc 0 col/row: 51 62
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 29 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 29 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 29 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 29 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 29 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 9
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 30 15
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 8
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 9
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 15
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 31 16
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 9
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 15
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 32 16
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 15
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 26
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 33 27
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 9
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 26
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 27
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 34 28
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 9
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 10
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 11
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 12
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 13
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 14
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 15
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 16
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 25
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 26
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 27
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 28
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 29
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 37
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 35 38
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 36 27
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 36 38
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 36 40
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 36 42
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 41
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 42
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 43
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 48
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 49
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 53
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 37 54
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 38 48
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 38 49
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 38 50
[16:36:52.840]     INFO: MASKED Roc 1 col/row: 38 51
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 38 52
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 38 53
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 38 54
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 51
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 52
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 53
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 54
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 55
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 56
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 57
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 39 58
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 40 53
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 40 57
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 40 58
[16:36:52.841]     INFO: MASKED Roc 1 col/row: 40 59
[16:36:52.841]     INFO: readTrimFile: data/mp315/trimParameters35_C0.dat .. data/mp315/trimParameters35_C15.dat
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 5
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 6
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 7
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 8
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 9
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 10
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 11
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 12
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 13
[16:36:52.846]     INFO:   masking Roc 0 col/row: 50 15
[16:36:52.846]     INFO:   masking Roc 0 col/row: 51 3
[16:36:52.846]     INFO:   masking Roc 0 col/row: 51 4
[16:36:52.846]     INFO:   masking Roc 0 col/row: 51 5
[16:36:52.846]     INFO:   masking Roc 0 col/row: 51 6
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 7
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 8
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 9
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 10
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 11
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 12
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 13
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 14
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 15
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 16
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 17
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 18
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 19
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 20
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 21
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 22
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 23
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 24
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 25
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 26
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 27
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 28
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 29
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 30
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 31
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 32
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 33
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 34
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 35
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 36
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 37
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 38
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 39
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 40
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 41
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 42
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 43
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 44
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 45
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 46
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 47
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 48
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 49
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 50
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 51
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 56
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 57
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 58
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 60
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 61
[16:36:52.847]     INFO:   masking Roc 0 col/row: 51 62
[16:36:52.859]     INFO:   masking Roc 1 col/row: 29 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 29 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 29 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 29 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 29 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 9
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 30 15
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 8
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 9
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 15
[16:36:52.859]     INFO:   masking Roc 1 col/row: 31 16
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 9
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 15
[16:36:52.859]     INFO:   masking Roc 1 col/row: 32 16
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 15
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 26
[16:36:52.859]     INFO:   masking Roc 1 col/row: 33 27
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 9
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 26
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 27
[16:36:52.859]     INFO:   masking Roc 1 col/row: 34 28
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 9
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 10
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 11
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 12
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 13
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 14
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 15
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 16
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 25
[16:36:52.859]     INFO:   masking Roc 1 col/row: 35 26
[16:36:52.860]     INFO:   masking Roc 1 col/row: 35 27
[16:36:52.860]     INFO:   masking Roc 1 col/row: 35 28
[16:36:52.860]     INFO:   masking Roc 1 col/row: 35 29
[16:36:52.860]     INFO:   masking Roc 1 col/row: 35 37
[16:36:52.860]     INFO:   masking Roc 1 col/row: 35 38
[16:36:52.860]     INFO:   masking Roc 1 col/row: 36 27
[16:36:52.860]     INFO:   masking Roc 1 col/row: 36 38
[16:36:52.860]     INFO:   masking Roc 1 col/row: 36 40
[16:36:52.860]     INFO:   masking Roc 1 col/row: 36 42
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 41
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 42
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 43
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 48
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 49
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 53
[16:36:52.860]     INFO:   masking Roc 1 col/row: 37 54
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 48
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 49
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 50
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 51
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 52
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 53
[16:36:52.860]     INFO:   masking Roc 1 col/row: 38 54
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 51
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 52
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 53
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 54
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 55
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 56
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 57
[16:36:52.860]     INFO:   masking Roc 1 col/row: 39 58
[16:36:52.860]     INFO:   masking Roc 1 col/row: 40 53
[16:36:52.860]     INFO:   masking Roc 1 col/row: 40 57
[16:36:52.860]     INFO:   masking Roc 1 col/row: 40 58
[16:36:52.860]     INFO:   masking Roc 1 col/row: 40 59
[16:36:53.001]     INFO:         clk: 4
[16:36:53.001]     INFO:         ctr: 4
[16:36:53.001]     INFO:         sda: 19
[16:36:53.001]     INFO:         tin: 9
[16:36:53.001]     INFO:         level: 15
[16:36:53.001]     INFO:         triggerdelay: 0
[16:36:53.001]    QUIET: Instanciating API for pxar v1.9.0+818~g9672706
[16:36:53.001]     INFO: Log level: DEBUG
[16:36:53.013]    QUIET: Connection to board DTB_WRPRHI opened.
[16:36:53.016]     INFO: DTB startup information
--- DTB info------------------------------------------
Board id:    58
HW version:  DTB1.2
FW version:  4.2
SW version:  4.5
USB id:      DTB_WRPRHI
MAC address: 40D85511803A
Hostname:    pixelDTB058
Comment:     
------------------------------------------------------
[16:36:53.019]     INFO: RPC call hashes of host and DTB match: 398089610
[16:36:54.623]     INFO: DUT info: 
[16:36:54.623]     INFO: The DUT currently contains the following objects:
[16:36:54.623]     INFO:  2 TBM Cores tbm08c (2 ON)
[16:36:54.623]     INFO: 	TBM Core alpha (0): 7 registers set
[16:36:54.623]     INFO: 	TBM Core beta  (1): 7 registers set
[16:36:54.623]     INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[16:36:54.623]     INFO: 	ROC 0: 19 DACs set, Pixels: 65 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 1: 19 DACs set, Pixels: 90 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.623]     INFO: 	ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.624]     INFO: 	ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.624]     INFO: 	ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB<-
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB2<-
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 222
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   plwidth: 35
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB3<-
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB4<-
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   savecaldelscan: checkbox(0)
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 100
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   cals: 1
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   caldello: 80
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelhi: 200
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelstep: 10
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomplo: 70
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomphi: 130
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompstep: 5
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   noisypixels: 10
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 255
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L107>   cut: 0.5
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Cmd<-
[16:36:54.624]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DAQ<-
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   trgnumber: 5
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqtrg: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   daqseconds: 5
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqseconds: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacDacScan<-
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1: caldel
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1lo: 0
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1hi: 255
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2: vthrcomp
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2lo: 0
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2hi: 255
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacScan<-
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox(1)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   allpixels: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   unmasked: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: vcal
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 255
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->GainPedestal<-
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   showfits: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   extended: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dumphists: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   vcalstep: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   measure: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   fit: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   save: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->HighRate<-
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixels: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixelthr: 200
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   runsecondshotpixels: 10
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   savetrimbits: checkbox(1)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   maskuntrimmable: checkbox(1)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelscan: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   xpixelalive: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   xnoisemaps: button
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 100
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: 20
[16:36:54.625]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaq: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 20
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 2
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   triggerdelay: 20
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->IV<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   port: /dev/FIXME
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestart: 0
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestop: 600
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestep: 5
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   delay: 1
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   compliance(ua): 100
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PhOptimization<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   safetymarginlow: 20
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   saturationvcal: 100
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   quantilesaturation: 0.98
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PixelAlive<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   alivetest: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   masktest: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   addressdecodingtest: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Pretest<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   programroc: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 100
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   settimings: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   findtiming: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   findworkingpixel: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   setvthrcompcaldel: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 250
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   deltavthrcomp: 50
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   fraccaldel: 0.5
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   savedacs: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Readback<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   calibratevd: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateva: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateia: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   readbackvbg: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   getcalibratedvbg: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalvd: checkbox(1)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalva: checkbox(0)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Scurves<-
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   adjustvcal: checkbox(0)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpoutputfile: checkbox(0)
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: Vcal
[16:36:54.626]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 200
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: -1
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig/step: -1
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   scurves: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Timing<-
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   targetclk: 4
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   clocksdascan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   notokenpass: checkbox(0)
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   phasescan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   levelscan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   tbmphasescan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   rocdelayscan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   timingtest: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   saveparameters: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Trim<-
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   trim: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 8
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 35
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   trimbits: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Xray<-
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   source: Ag
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   phrun: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 100
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   ratescan: button
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmin: 10
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmax: 80
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   stepseconds: 5
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:36:54.627]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L81> PixSetup init start; getCurrentRSS() = 31657984
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L87> fPixTestParameters = 0xfad0b0
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L88>  fConfigParameters = 0xd4f370
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L89>        fPxarMemory = 0x7ffb8bd83010
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L90>         fPxarMemHi = 0x7ffb91fee510
[16:36:54.629]    DEBUG: <PixSetup.cc/init:L106> PixSetup init done;  getCurrentRSS() = 31666176 fPxarMemory = 0x7ffb8bd83010
[16:36:54.631]    DEBUG: <pXar.cc/main:L223> Initial Analog Current: 394.7mA
[16:36:54.632]    DEBUG: <pXar.cc/main:L224> Initial Digital Current: 471.1mA
[16:36:54.632]    DEBUG: <pXar.cc/main:L225> Initial Module Temperature: -0.1 C
[16:36:55.128]    DEBUG: <PixGui.cc/hvOn:L460> HV set On: 0x139c430
[16:36:55.191]    DEBUG: <PixTestFactory.cc/PixTestFactory:L53> PixTestFactory::PixTestFactory()
[16:36:55.191]    DEBUG: <PixTestBBMap.cc/init:L79> PixTestBBMap::init()
[16:36:55.191]    DEBUG: <PixTestBBMap.cc/PixTestBBMap:L27> PixTestBBMap ctor(PixSetup &a, string, TGTab *)
[16:36:55.197]    DEBUG: <PixTestBB2Map.cc/setParameter:L58> setting fTargetIa    = 24 mA/ROC
[16:36:55.197]    DEBUG: <PixTestBB2Map.cc/init:L97> PixTestBB2Map::init()
[16:36:55.197]    DEBUG: <PixTestBB2Map.cc/PixTestBB2Map:L29> PixTestBB2Map ctor(PixSetup &a, string, TGTab *)
[16:36:55.207]    DEBUG: <PixTestBB3Map.cc/init:L81> PixTestBB3Map::init()
[16:36:55.207]    DEBUG: <PixTestBB3Map.cc/PixTestBB3Map:L29> PixTestBB3Map ctor(PixSetup &a, string, TGTab *)
[16:36:55.214]    DEBUG: <PixTestBB4Map.cc/init:L93> PixTestBB4Map::init()
[16:36:55.214]    DEBUG: <PixTestBB4Map.cc/PixTestBB4Map:L26> PixTestMapeff ctor(PixSetup &a, string, TGTab *)
[16:36:55.234]     INFO: PixTestCmd::init()
[16:36:55.247]    DEBUG: <PixTestDaq.cc/init:L44> PixTestDaq::init()
[16:36:55.247]    DEBUG: <PixTestDaq.cc/PixTestDaq:L22> PixTestDaq ctor(PixSetup &a, string, TGTab *)
[16:36:55.247]     INFO: readGainPedestalParameters data/mp315/phCalibrationFitErr35_C0.dat .. data/mp315/phCalibrationFitErr35_C15.dat
[16:36:55.500]    DEBUG: <PixTestDacDacScan.cc/init:L103> PixTestDacDacScan::init()
[16:36:55.500]    DEBUG: <PixTestDacDacScan.cc/PixTestDacDacScan:L22> PixTestDacDacScan ctor(PixSetup &a, string, TGTab *)
[16:36:55.519]    DEBUG: <PixTestGainPedestal.cc/setParameter:L83> PixTestGainPedestal::PixTest() fVcalStep = 10
[16:36:55.529]    DEBUG: <PixTestHighRate.cc/setParameter:L68>   setting fParTriggerFrequency -> 20
[16:36:55.529]    DEBUG: <PixTestHighRate.cc/init:L211> PixTestHighRate::init()
[16:36:55.529]    DEBUG: <PixTestHighRate.cc/PixTestHighRate:L31> PixTestHighRate ctor(PixSetup &a, string, TGTab *)
[16:36:55.555]    DEBUG: <PixTest.cc/setTestParameter:L637>  setting  ntrig to new value 10
[16:36:55.555]    DEBUG: <PixTestPhOptimization.cc/setParameter:L37>   setting fParNtrig  ->10<- from sval = 10
[16:36:55.555]    DEBUG: <PixTestPhOptimization.cc/setParameter:L42>   setting fSafetyMarginLow  ->20<- from sval = 20
[16:36:55.555]    DEBUG: <PixTestPhOptimization.cc/setParameter:L48>   setting fVcalMax  ->100<- from sval = 100
[16:36:55.555]    DEBUG: <PixTestPhOptimization.cc/setParameter:L53>   setting fQuantMax  ->0.98<- from sval = 0.98
[16:36:55.561]    DEBUG: <PixTestAlive.cc/init:L83> PixTestAlive::init()
[16:36:55.562]    DEBUG: <PixTestAlive.cc/PixTestAlive:L21> PixTestAlive ctor(PixSetup &a, string, TGTab *)
[16:36:55.586]    DEBUG: <PixTestReadback.cc/setParameter:L172> fCalwVd set to 1
[16:36:55.586]    DEBUG: <PixTestReadback.cc/init:L95> PixTestReadback::init()
[16:36:55.586]    DEBUG: <PixTestReadback.cc/PixTestReadback:L22> PixTestReadback ctor(PixSetup &a, string, TGTab *)
[16:36:55.586]     INFO: readReadbackCal: data/mp315/readbackCal_C0.dat .. data/mp315/readbackCal_C15.dat
[16:36:55.602]    DEBUG: <PixTestScurves.cc/setParameter:L93> set fOutputFilename = 
[16:36:55.610]    DEBUG: <PixTestTiming.cc/setParameter:L59> PixTestTiming::PixTest() targetclk = 4
[16:36:55.611]    DEBUG: <PixTestTiming.cc/setParameter:L63> PixTestTiming::PixTest() ntrig = 10
[16:36:55.611]    DEBUG: <PixTestTiming.cc/setParameter:L47> fNoTokenPass: 0
[16:36:55.611]    DEBUG: <PixTestTiming.cc/init:L73> PixTestTiming::init()
[16:36:55.625]    DEBUG: <PixTestXray.cc/init:L135> PixTestXray::init()
[16:36:55.625]    DEBUG: <PixTestXray.cc/PixTestXray:L28> PixTestXray ctor(PixSetup &a, string, TGTab *)
[16:36:59.578]     INFO: ######################################################################
[16:36:59.578]     INFO: PixTestXray::doTest()
[16:36:59.578]     INFO: ######################################################################
[16:36:59.578]     INFO:    ----------------------------------------------------------------------
[16:36:59.578]     INFO:    PixTestXray::doPhRun() fParRunSeconds = 100
[16:36:59.578]     INFO:    ----------------------------------------------------------------------
[16:36:59.581]     INFO: ROC 0 masking hot pixel 50/5
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[16:36:59.587]     INFO: ROC 1 masking pixel 32/15
[16:36:59.587]     INFO: ROC 1 masking pixel 32/16
[16:36:59.587]     INFO: ROC 1 masking pixel 33/10
[16:36:59.587]     INFO: ROC 1 masking pixel 33/11
[16:36:59.587]     INFO: ROC 1 masking pixel 33/12
[16:36:59.587]     INFO: ROC 1 masking pixel 33/13
[16:36:59.587]     INFO: ROC 1 masking pixel 33/14
[16:36:59.587]     INFO: ROC 1 masking pixel 33/15
[16:36:59.587]     INFO: ROC 1 masking pixel 33/26
[16:36:59.587]     INFO: ROC 1 masking pixel 33/27
[16:36:59.587]     INFO: ROC 1 masking pixel 34/9
[16:36:59.587]     INFO: ROC 1 masking pixel 34/10
[16:36:59.587]     INFO: ROC 1 masking pixel 34/11
[16:36:59.587]     INFO: ROC 1 masking pixel 34/12
[16:36:59.587]     INFO: ROC 1 masking pixel 34/13
[16:36:59.587]     INFO: ROC 1 masking pixel 34/26
[16:36:59.587]     INFO: ROC 1 masking pixel 34/27
[16:36:59.587]     INFO: ROC 1 masking pixel 34/28
[16:36:59.587]     INFO: ROC 1 masking pixel 35/9
[16:36:59.587]     INFO: ROC 1 masking pixel 35/10
[16:36:59.587]     INFO: ROC 1 masking pixel 35/11
[16:36:59.587]     INFO: ROC 1 masking pixel 35/12
[16:36:59.587]     INFO: ROC 1 masking pixel 35/13
[16:36:59.587]     INFO: ROC 1 masking pixel 35/14
[16:36:59.587]     INFO: ROC 1 masking pixel 35/15
[16:36:59.587]     INFO: ROC 1 masking pixel 35/16
[16:36:59.587]     INFO: ROC 1 masking pixel 35/25
[16:36:59.587]     INFO: ROC 1 masking pixel 35/26
[16:36:59.587]     INFO: ROC 1 masking pixel 35/27
[16:36:59.587]     INFO: ROC 1 masking pixel 35/28
[16:36:59.587]     INFO: ROC 1 masking pixel 35/29
[16:36:59.587]     INFO: ROC 1 masking pixel 35/37
[16:36:59.587]     INFO: ROC 1 masking pixel 35/38
[16:36:59.587]     INFO: ROC 1 masking pixel 36/27
[16:36:59.587]     INFO: ROC 1 masking pixel 36/38
[16:36:59.587]     INFO: ROC 1 masking pixel 36/40
[16:36:59.587]     INFO: ROC 1 masking pixel 36/42
[16:36:59.587]     INFO: ROC 1 masking pixel 37/41
[16:36:59.587]     INFO: ROC 1 masking pixel 37/42
[16:36:59.588]     INFO: ROC 1 masking pixel 37/43
[16:36:59.588]     INFO: ROC 1 masking pixel 37/48
[16:36:59.588]     INFO: ROC 1 masking pixel 37/49
[16:36:59.588]     INFO: ROC 1 masking pixel 37/53
[16:36:59.588]     INFO: ROC 1 masking pixel 37/54
[16:36:59.588]     INFO: ROC 1 masking pixel 38/48
[16:36:59.588]     INFO: ROC 1 masking pixel 38/49
[16:36:59.588]     INFO: ROC 1 masking pixel 38/50
[16:36:59.588]     INFO: ROC 1 masking pixel 38/51
[16:36:59.588]     INFO: ROC 1 masking pixel 38/52
[16:36:59.588]     INFO: ROC 1 masking pixel 38/53
[16:36:59.588]     INFO: ROC 1 masking pixel 38/54
[16:36:59.588]     INFO: ROC 1 masking pixel 39/51
[16:36:59.588]     INFO: ROC 1 masking pixel 39/52
[16:36:59.588]     INFO: ROC 1 masking pixel 39/53
[16:36:59.588]     INFO: ROC 1 masking pixel 39/54
[16:36:59.588]     INFO: ROC 1 masking pixel 39/55
[16:36:59.588]     INFO: ROC 1 masking pixel 39/56
[16:36:59.588]     INFO: ROC 1 masking pixel 39/57
[16:36:59.588]     INFO: ROC 1 masking pixel 39/58
[16:36:59.588]     INFO: ROC 1 masking pixel 40/53
[16:36:59.588]     INFO: ROC 1 masking pixel 40/57
[16:36:59.588]     INFO: ROC 1 masking pixel 40/58
[16:36:59.588]     INFO: ROC 1 masking pixel 40/59
[16:37:00.559]     INFO: PixTestXray::doPhRun start TriggerLoop with trigger frequency 100 kHz, period 405 and duration 100 seconds,  fEventsMax = 10000000
[16:37:08.648]     INFO: run duration 8 seconds, buffer almost full (81%), pausing triggers.
[16:37:08.652]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:37:34.257]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 797031 events.
[16:37:45.923]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 797031, pixels seen in all events: 10675059
[16:37:46.208]     INFO: Resuming triggers.
[16:37:54.284]     INFO: run duration 16 seconds, buffer almost full (81%), pausing triggers.
[16:37:54.322]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:38:19.973]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 795590 events.
[16:38:31.632]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 795590, pixels seen in all events: 10691536
[16:38:31.826]     INFO: Resuming triggers.
[16:38:39.909]     INFO: run duration 24 seconds, buffer almost full (81%), pausing triggers.
[16:38:39.950]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:39:05.481]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796290 events.
[16:39:17.129]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796290, pixels seen in all events: 10683622
[16:39:17.341]     INFO: Resuming triggers.
[16:39:25.423]     INFO: run duration 32 seconds, buffer almost full (81%), pausing triggers.
[16:39:25.501]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:39:51.074]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796218 events.
[16:40:02.788]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796218, pixels seen in all events: 10684658
[16:40:03.048]     INFO: Resuming triggers.
[16:40:11.134]     INFO: run duration 40 seconds, buffer almost full (81%), pausing triggers.
[16:40:11.181]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:40:36.681]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796589 events.
[16:40:48.478]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796589, pixels seen in all events: 10679868
[16:40:48.689]     INFO: Resuming triggers.
[16:40:56.777]     INFO: run duration 48 seconds, buffer almost full (81%), pausing triggers.
[16:40:56.821]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:41:22.317]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796708 events.
[16:41:33.996]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796708, pixels seen in all events: 10678143
[16:41:34.216]     INFO: Resuming triggers.
[16:41:42.304]     INFO: run duration 56 seconds, buffer almost full (81%), pausing triggers.
[16:41:42.377]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:42:08.040]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796772 events.
[16:42:20.932]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796772, pixels seen in all events: 10677715
[16:42:21.194]     INFO: Resuming triggers.
[16:42:29.284]     INFO: run duration 64 seconds, buffer almost full (81%), pausing triggers.
[16:42:29.329]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:42:54.869]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796959 events.
[16:43:06.569]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796959, pixels seen in all events: 10675592
[16:43:06.785]     INFO: Resuming triggers.
[16:43:14.873]     INFO: run duration 72 seconds, buffer almost full (81%), pausing triggers.
[16:43:14.954]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:43:40.493]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796797 events.
[16:43:52.218]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796797, pixels seen in all events: 10677298
[16:43:52.476]     INFO: Resuming triggers.
[16:44:00.565]     INFO: run duration 80 seconds, buffer almost full (81%), pausing triggers.
[16:44:00.594]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:44:26.045]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796918 events.
[16:44:37.792]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796918, pixels seen in all events: 10675827
[16:44:38.055]     INFO: Resuming triggers.
[16:44:46.146]     INFO: run duration 88 seconds, buffer almost full (81%), pausing triggers.
[16:44:46.187]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:45:11.690]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 797117 events.
[16:45:23.435]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 797117, pixels seen in all events: 10673185
[16:45:23.652]     INFO: Resuming triggers.
[16:45:31.740]     INFO: run duration 96 seconds, buffer almost full (81%), pausing triggers.
[16:45:31.788]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:45:57.380]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 796698 events.
[16:46:09.175]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 796698, pixels seen in all events: 10678058
[16:46:09.440]     INFO: Resuming triggers.
[16:46:12.536]     INFO: data taking finished, elapsed time: 100 seconds.
[16:46:12.733]    DEBUG: <PixTestXray.cc/processData:L754> Getting Event Buffer
[16:46:22.690]    DEBUG: <PixTestXray.cc/processData:L772> Processing Data: 305016 events.
[16:46:27.170]    DEBUG: <PixTestXray.cc/processData:L823>  # events read: 305016, pixels seen in all events: 4081912
[16:46:27.255]     INFO: PixTest::       pg_setup set to default.
[16:46:27.300]     INFO: PixTestXray::doPhRun() done
[16:46:27.300]     INFO: PixTestXray::doTest() done 
[16:46:54.122]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:46:54.122]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = hMap_Ag_C13_V0 -> hMap_Ag_mod
[16:46:55.962]    DEBUG: <PixGui.cc/handleButtons:L396> PixGui::exit called
[16:46:55.963]    DEBUG: <PixGui.cc/CloseWindow:L335> Final Analog Current: 398.7mA
[16:46:55.964]    DEBUG: <PixGui.cc/CloseWindow:L336> Final Digital Current: 471.1mA
[16:46:55.964]    DEBUG: <PixGui.cc/CloseWindow:L337> Final Module Temperature: -0.2 C
[16:46:55.964]    DEBUG: <PixTestBBMap.cc/~PixTestBBMap:L97> PixTestBBMap dtor
[16:46:55.964]    DEBUG: <PixTestBB2Map.cc/~PixTestBB2Map:L115> PixTestBB2Map dtor
[16:46:55.964]    DEBUG: <PixTestBB3Map.cc/~PixTestBB3Map:L99> PixTestBB3Map dtor
[16:46:55.964]    DEBUG: <PixTestBB4Map.cc/~PixTestBB4Map:L118> PixTestBB4Map dtor
[16:46:55.964]    DEBUG: <PixTestCmd.cc/~PixTestCmd:L78> PixTestCmd dtor
[16:46:55.964]    DEBUG: <PixTestDaq.cc/~PixTestDaq:L37> PixTestDaq dtor
[16:46:55.964]    DEBUG: <PixTestDacDacScan.cc/~PixTestDacDacScan:L136> PixTestDacDacScan dtor
[16:46:55.964]    DEBUG: <PixTestDacScan.cc/~PixTestDacScan:L129> PixTestDacScan dtor
[16:46:55.964]    DEBUG: <PixTestGainPedestal.cc/~PixTestGainPedestal:L125> PixTestGainPedestal dtor
[16:46:55.964]    DEBUG: <PixTestHighRate.cc/~PixTestHighRate:L258> PixTestHighRate dtor
[16:46:55.965]    DEBUG: <PixTestIV.cc/~PixTestIV:L96> PixTestIV dtor
[16:46:55.965]    DEBUG: <PixTestAlive.cc/~PixTestAlive:L115> PixTestAlive dtor
[16:46:55.965]    DEBUG: <PixTestPretest.cc/~PixTestPretest:L136> PixTestPretest dtor
[16:46:55.965]    DEBUG: <PixTestReadback.cc/~PixTestReadback:L89> PixTestReadback dtor, saving tree ... 
[16:46:55.965]    DEBUG: <PixTestScurves.cc/~PixTestScurves:L142> PixTestScurves dtor
[16:46:55.965]    DEBUG: <PixTestTiming.cc/~PixTestTiming:L96> PixTestTiming dtor
[16:46:55.965]    DEBUG: <PixTestTrim.cc/~PixTestTrim:L103> PixTestTrim dtor
[16:46:55.965]    DEBUG: <PixTestXray.cc/~PixTestXray:L218> PixTestXray dtor
[16:46:56.297]    QUIET: Connection to board 58 closed.
[16:46:56.377]    DEBUG: <PixMonitor.cc/dumpSummaries:L39> PixMonitor::dumpSummaries
									 
									
									
															
						
							
						
						[16:20:01.453]     INFO: *** Welcome to pxar ***
[16:20:01.453]     INFO: *** Today: 2016/09/07
[16:20:01.478]     INFO: *** Version: v1.9.0-818-g96727
[16:20:01.478]     INFO: readRocDacs: data/mp315/dacParameters35_C0.dat .. data/mp315/dacParameters35_C15.dat
[16:20:01.479]     INFO: readTbmDacs: data/mp315/tbmParameters_C0a.dat .. data/mp315/tbmParameters_C0b.dat
[16:20:01.479]     INFO: readMaskFile: data/mp315/defaultMaskFile.dat
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 5
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 6
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 7
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 8
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 9
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 10
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 11
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 12
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 13
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 50 15
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 3
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 4
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 5
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 6
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 7
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 8
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 9
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 10
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 11
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 12
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 13
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 14
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 15
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 16
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 17
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 18
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 19
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 20
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 21
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 22
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 23
[16:20:01.479]     INFO: MASKED Roc 0 col/row: 51 24
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 25
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 26
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 27
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 28
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 29
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 30
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 31
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 32
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 33
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 34
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 35
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 36
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 37
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 38
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 39
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 40
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 41
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 42
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 43
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 44
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 45
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 46
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 47
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 48
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 49
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 50
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 51
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 56
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 57
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 58
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 60
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 61
[16:20:01.480]     INFO: MASKED Roc 0 col/row: 51 62
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 29 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 29 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 29 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 29 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 29 14
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 9
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 14
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 30 15
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 8
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 9
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 14
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 15
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 31 16
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 9
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 14
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 15
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 32 16
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 14
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 15
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 26
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 33 27
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 9
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 11
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 12
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 13
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 26
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 27
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 34 28
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 35 9
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 35 10
[16:20:01.480]     INFO: MASKED Roc 1 col/row: 35 11
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 12
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 13
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 14
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 15
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 16
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 25
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 26
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 27
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 28
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 29
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 37
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 35 38
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 36 27
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 36 38
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 36 40
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 36 42
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 41
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 42
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 43
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 48
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 49
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 53
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 37 54
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 48
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 49
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 50
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 51
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 52
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 53
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 38 54
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 39 51
[16:20:01.481]     INFO: MASKED Roc 1 col/row: 39 52
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 53
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 54
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 55
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 56
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 57
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 39 58
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 40 53
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 40 57
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 40 58
[16:20:01.482]     INFO: MASKED Roc 1 col/row: 40 59
[16:20:01.482]     INFO: readTrimFile: data/mp315/trimParameters35_C0.dat .. data/mp315/trimParameters35_C15.dat
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 5
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 6
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 7
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 8
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 9
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 10
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 11
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 12
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 13
[16:20:01.483]     INFO:   masking Roc 0 col/row: 50 15
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 3
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 4
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 5
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 6
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 7
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 8
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 9
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 10
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 11
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 12
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 13
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 14
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 15
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 16
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 17
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 18
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 19
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 20
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 21
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 22
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 23
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 24
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 25
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 26
[16:20:01.483]     INFO:   masking Roc 0 col/row: 51 27
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 28
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 29
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 30
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 31
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 32
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 33
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 34
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 35
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 36
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 37
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 38
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 39
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 40
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 41
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 42
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 43
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 44
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 45
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 46
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 47
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 48
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 49
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 50
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 51
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 56
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 57
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 58
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 60
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 61
[16:20:01.484]     INFO:   masking Roc 0 col/row: 51 62
[16:20:01.494]     INFO:   masking Roc 1 col/row: 29 10
[16:20:01.494]     INFO:   masking Roc 1 col/row: 29 11
[16:20:01.494]     INFO:   masking Roc 1 col/row: 29 12
[16:20:01.494]     INFO:   masking Roc 1 col/row: 29 13
[16:20:01.494]     INFO:   masking Roc 1 col/row: 29 14
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 9
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 10
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 11
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 12
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 13
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 14
[16:20:01.494]     INFO:   masking Roc 1 col/row: 30 15
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 8
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 9
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 10
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 11
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 12
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 13
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 14
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 15
[16:20:01.494]     INFO:   masking Roc 1 col/row: 31 16
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 9
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 10
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 11
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 12
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 13
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 14
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 15
[16:20:01.494]     INFO:   masking Roc 1 col/row: 32 16
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 10
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 11
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 12
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 13
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 14
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 15
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 26
[16:20:01.495]     INFO:   masking Roc 1 col/row: 33 27
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 9
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 10
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 11
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 12
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 13
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 26
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 27
[16:20:01.495]     INFO:   masking Roc 1 col/row: 34 28
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 9
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 10
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 11
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 12
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 13
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 14
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 15
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 16
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 25
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 26
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 27
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 28
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 29
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 37
[16:20:01.495]     INFO:   masking Roc 1 col/row: 35 38
[16:20:01.495]     INFO:   masking Roc 1 col/row: 36 27
[16:20:01.495]     INFO:   masking Roc 1 col/row: 36 38
[16:20:01.495]     INFO:   masking Roc 1 col/row: 36 40
[16:20:01.495]     INFO:   masking Roc 1 col/row: 36 42
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 41
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 42
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 43
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 48
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 49
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 53
[16:20:01.495]     INFO:   masking Roc 1 col/row: 37 54
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 48
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 49
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 50
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 51
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 52
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 53
[16:20:01.495]     INFO:   masking Roc 1 col/row: 38 54
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 51
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 52
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 53
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 54
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 55
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 56
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 57
[16:20:01.495]     INFO:   masking Roc 1 col/row: 39 58
[16:20:01.495]     INFO:   masking Roc 1 col/row: 40 53
[16:20:01.495]     INFO:   masking Roc 1 col/row: 40 57
[16:20:01.496]     INFO:   masking Roc 1 col/row: 40 58
[16:20:01.496]     INFO:   masking Roc 1 col/row: 40 59
[16:20:01.635]     INFO:         clk: 4
[16:20:01.635]     INFO:         ctr: 4
[16:20:01.635]     INFO:         sda: 19
[16:20:01.635]     INFO:         tin: 9
[16:20:01.635]     INFO:         level: 15
[16:20:01.635]     INFO:         triggerdelay: 0
[16:20:01.635]    QUIET: Instanciating API for pxar v1.9.0+818~g9672706
[16:20:01.635]     INFO: Log level: DEBUG
[16:20:01.646]    QUIET: Connection to board DTB_WRPRHI opened.
[16:20:01.650]     INFO: DTB startup information
--- DTB info------------------------------------------
Board id:    58
HW version:  DTB1.2
FW version:  4.2
SW version:  4.5
USB id:      DTB_WRPRHI
MAC address: 40D85511803A
Hostname:    pixelDTB058
Comment:     
------------------------------------------------------
[16:20:01.652]     INFO: RPC call hashes of host and DTB match: 398089610
[16:20:03.256]     INFO: DUT info: 
[16:20:03.256]     INFO: The DUT currently contains the following objects:
[16:20:03.256]     INFO:  2 TBM Cores tbm08c (2 ON)
[16:20:03.256]     INFO: 	TBM Core alpha (0): 7 registers set
[16:20:03.256]     INFO: 	TBM Core beta  (1): 7 registers set
[16:20:03.256]     INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[16:20:03.256]     INFO: 	ROC 0: 19 DACs set, Pixels: 65 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 1: 19 DACs set, Pixels: 90 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.256]     INFO: 	ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.257]     INFO: 	ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB2<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 222
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   plwidth: 35
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB3<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB4<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   savecaldelscan: checkbox(0)
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 100
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   cals: 1
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   caldello: 80
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelhi: 200
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelstep: 10
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomplo: 70
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomphi: 130
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompstep: 5
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   noisypixels: 10
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 255
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   cut: 0.5
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Cmd<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DAQ<-
[16:20:03.257]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   trgnumber: 5
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqtrg: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   daqseconds: 5
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqseconds: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacDacScan<-
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1: caldel
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1lo: 0
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1hi: 255
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2: vthrcomp
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2lo: 0
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2hi: 255
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacScan<-
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox(1)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   allpixels: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   unmasked: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: vcal
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 255
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->GainPedestal<-
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   showfits: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   extended: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dumphists: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   vcalstep: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   measure: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   fit: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   save: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->HighRate<-
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixels: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixelthr: 200
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   runsecondshotpixels: 10
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   savetrimbits: checkbox(1)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   maskuntrimmable: checkbox(1)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelscan: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   xpixelalive: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   xnoisemaps: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 100
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: 20
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaq: button
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 20
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 2
[16:20:03.258]    DEBUG: <PixTestParameters.cc/dump:L107>   triggerdelay: 20
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->IV<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   port: /dev/FIXME
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestart: 0
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestop: 600
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestep: 5
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   delay: 1
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   compliance(ua): 100
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PhOptimization<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   safetymarginlow: 20
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   saturationvcal: 100
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   quantilesaturation: 0.98
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PixelAlive<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   alivetest: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   masktest: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   addressdecodingtest: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Pretest<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   programroc: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 100
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   settimings: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   findtiming: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   findworkingpixel: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   setvthrcompcaldel: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 250
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   deltavthrcomp: 50
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   fraccaldel: 0.5
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   savedacs: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Readback<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   calibratevd: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateva: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateia: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   readbackvbg: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   getcalibratedvbg: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalvd: checkbox(1)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalva: checkbox(0)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Scurves<-
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   adjustvcal: checkbox(0)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpoutputfile: checkbox(0)
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: Vcal
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 200
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: -1
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig/step: -1
[16:20:03.259]    DEBUG: <PixTestParameters.cc/dump:L107>   scurves: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Timing<-
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   targetclk: 4
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   clocksdascan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   notokenpass: checkbox(0)
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   phasescan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   levelscan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   tbmphasescan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   rocdelayscan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   timingtest: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   saveparameters: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Trim<-
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   trim: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 8
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 35
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   trimbits: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Xray<-
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   source: Ag
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   phrun: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 100
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   ratescan: button
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmin: 10
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmax: 80
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   stepseconds: 5
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:20:03.260]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L81> PixSetup init start; getCurrentRSS() = 33411072
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L87> fPixTestParameters = 0x25320b0
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L88>  fConfigParameters = 0x22d4370
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L89>        fPxarMemory = 0x7f4d85d94010
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L90>         fPxarMemHi = 0x7f4d8bfff510
[16:20:03.262]    DEBUG: <PixSetup.cc/init:L106> PixSetup init done;  getCurrentRSS() = 33419264 fPxarMemory = 0x7f4d85d94010
[16:20:03.263]    DEBUG: <pXar.cc/main:L223> Initial Analog Current: 394.7mA
[16:20:03.265]    DEBUG: <pXar.cc/main:L224> Initial Digital Current: 471.1mA
[16:20:03.265]    DEBUG: <pXar.cc/main:L225> Initial Module Temperature: -0.2 C
[16:20:03.765]    DEBUG: <PixGui.cc/hvOn:L460> HV set On: 0x29213d0
[16:20:03.829]    DEBUG: <PixTestFactory.cc/PixTestFactory:L53> PixTestFactory::PixTestFactory()
[16:20:03.829]    DEBUG: <PixTestBBMap.cc/init:L79> PixTestBBMap::init()
[16:20:03.830]    DEBUG: <PixTestBBMap.cc/PixTestBBMap:L27> PixTestBBMap ctor(PixSetup &a, string, TGTab *)
[16:20:03.836]    DEBUG: <PixTestBB2Map.cc/setParameter:L58> setting fTargetIa    = 24 mA/ROC
[16:20:03.836]    DEBUG: <PixTestBB2Map.cc/init:L97> PixTestBB2Map::init()
[16:20:03.836]    DEBUG: <PixTestBB2Map.cc/PixTestBB2Map:L29> PixTestBB2Map ctor(PixSetup &a, string, TGTab *)
[16:20:03.847]    DEBUG: <PixTestBB3Map.cc/init:L81> PixTestBB3Map::init()
[16:20:03.847]    DEBUG: <PixTestBB3Map.cc/PixTestBB3Map:L29> PixTestBB3Map ctor(PixSetup &a, string, TGTab *)
[16:20:03.865]    DEBUG: <PixTestBB4Map.cc/init:L93> PixTestBB4Map::init()
[16:20:03.865]    DEBUG: <PixTestBB4Map.cc/PixTestBB4Map:L26> PixTestMapeff ctor(PixSetup &a, string, TGTab *)
[16:20:03.880]     INFO: PixTestCmd::init()
[16:20:03.893]    DEBUG: <PixTestDaq.cc/init:L44> PixTestDaq::init()
[16:20:03.893]    DEBUG: <PixTestDaq.cc/PixTestDaq:L22> PixTestDaq ctor(PixSetup &a, string, TGTab *)
[16:20:03.893]     INFO: readGainPedestalParameters data/mp315/phCalibrationFitErr35_C0.dat .. data/mp315/phCalibrationFitErr35_C15.dat
[16:20:04.151]    DEBUG: <PixTestDacDacScan.cc/init:L103> PixTestDacDacScan::init()
[16:20:04.151]    DEBUG: <PixTestDacDacScan.cc/PixTestDacDacScan:L22> PixTestDacDacScan ctor(PixSetup &a, string, TGTab *)
[16:20:04.165]    DEBUG: <PixTestGainPedestal.cc/setParameter:L83> PixTestGainPedestal::PixTest() fVcalStep = 10
[16:20:04.172]    DEBUG: <PixTestHighRate.cc/setParameter:L68>   setting fParTriggerFrequency -> 20
[16:20:04.172]    DEBUG: <PixTestHighRate.cc/init:L211> PixTestHighRate::init()
[16:20:04.172]    DEBUG: <PixTestHighRate.cc/PixTestHighRate:L31> PixTestHighRate ctor(PixSetup &a, string, TGTab *)
[16:20:04.196]    DEBUG: <PixTest.cc/setTestParameter:L637>  setting  ntrig to new value 10
[16:20:04.196]    DEBUG: <PixTestPhOptimization.cc/setParameter:L37>   setting fParNtrig  ->10<- from sval = 10
[16:20:04.196]    DEBUG: <PixTestPhOptimization.cc/setParameter:L42>   setting fSafetyMarginLow  ->20<- from sval = 20
[16:20:04.196]    DEBUG: <PixTestPhOptimization.cc/setParameter:L48>   setting fVcalMax  ->100<- from sval = 100
[16:20:04.196]    DEBUG: <PixTestPhOptimization.cc/setParameter:L53>   setting fQuantMax  ->0.98<- from sval = 0.98
[16:20:04.202]    DEBUG: <PixTestAlive.cc/init:L83> PixTestAlive::init()
[16:20:04.202]    DEBUG: <PixTestAlive.cc/PixTestAlive:L21> PixTestAlive ctor(PixSetup &a, string, TGTab *)
[16:20:04.227]    DEBUG: <PixTestReadback.cc/setParameter:L172> fCalwVd set to 1
[16:20:04.227]    DEBUG: <PixTestReadback.cc/init:L95> PixTestReadback::init()
[16:20:04.227]    DEBUG: <PixTestReadback.cc/PixTestReadback:L22> PixTestReadback ctor(PixSetup &a, string, TGTab *)
[16:20:04.227]     INFO: readReadbackCal: data/mp315/readbackCal_C0.dat .. data/mp315/readbackCal_C15.dat
[16:20:04.237]    DEBUG: <PixTestScurves.cc/setParameter:L93> set fOutputFilename = 
[16:20:04.245]    DEBUG: <PixTestTiming.cc/setParameter:L59> PixTestTiming::PixTest() targetclk = 4
[16:20:04.245]    DEBUG: <PixTestTiming.cc/setParameter:L63> PixTestTiming::PixTest() ntrig = 10
[16:20:04.245]    DEBUG: <PixTestTiming.cc/setParameter:L47> fNoTokenPass: 0
[16:20:04.245]    DEBUG: <PixTestTiming.cc/init:L73> PixTestTiming::init()
[16:20:04.263]    DEBUG: <PixTestXray.cc/init:L135> PixTestXray::init()
[16:20:04.263]    DEBUG: <PixTestXray.cc/PixTestXray:L28> PixTestXray ctor(PixSetup &a, string, TGTab *)
[16:20:08.373]     INFO: ######################################################################
[16:20:08.373]     INFO: PixTestAlive::doTest()
[16:20:08.373]     INFO: ######################################################################
[16:20:08.377]     INFO:    ----------------------------------------------------------------------
[16:20:08.377]     INFO:    PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:20:08.377]     INFO:    ----------------------------------------------------------------------
[16:20:08.379]     INFO: ROC 0 masking pixel 50/5
[16:20:08.379]     INFO: ROC 0 masking pixel 50/6
[16:20:08.379]     INFO: ROC 0 masking pixel 50/7
[16:20:08.379]     INFO: ROC 0 masking pixel 50/8
[16:20:08.379]     INFO: ROC 0 masking pixel 50/9
[16:20:08.379]     INFO: ROC 0 masking pixel 50/10
[16:20:08.379]     INFO: ROC 0 masking pixel 50/11
[16:20:08.379]     INFO: ROC 0 masking pixel 50/12
[16:20:08.379]     INFO: ROC 0 masking pixel 50/13
[16:20:08.379]     INFO: ROC 0 masking pixel 50/15
[16:20:08.379]     INFO: ROC 0 masking pixel 51/3
[16:20:08.379]     INFO: ROC 0 masking pixel 51/4
[16:20:08.379]     INFO: ROC 0 masking pixel 51/5
[16:20:08.379]     INFO: ROC 0 masking pixel 51/6
[16:20:08.379]     INFO: ROC 0 masking pixel 51/7
[16:20:08.379]     INFO: ROC 0 masking pixel 51/8
[16:20:08.379]     INFO: ROC 0 masking pixel 51/9
[16:20:08.379]     INFO: ROC 0 masking pixel 51/10
[16:20:08.379]     INFO: ROC 0 masking pixel 51/11
[16:20:08.379]     INFO: ROC 0 masking pixel 51/12
[16:20:08.379]     INFO: ROC 0 masking pixel 51/13
[16:20:08.379]     INFO: ROC 0 masking pixel 51/14
[16:20:08.379]     INFO: ROC 0 masking pixel 51/15
[16:20:08.380]     INFO: ROC 0 masking pixel 51/16
[16:20:08.380]     INFO: ROC 0 masking pixel 51/17
[16:20:08.380]     INFO: ROC 0 masking pixel 51/18
[16:20:08.380]     INFO: ROC 0 masking pixel 51/19
[16:20:08.380]     INFO: ROC 0 masking pixel 51/20
[16:20:08.380]     INFO: ROC 0 masking pixel 51/21
[16:20:08.380]     INFO: ROC 0 masking pixel 51/22
[16:20:08.380]     INFO: ROC 0 masking pixel 51/23
[16:20:08.380]     INFO: ROC 0 masking pixel 51/24
[16:20:08.380]     INFO: ROC 0 masking pixel 51/25
[16:20:08.380]     INFO: ROC 0 masking pixel 51/26
[16:20:08.380]     INFO: ROC 0 masking pixel 51/27
[16:20:08.380]     INFO: ROC 0 masking pixel 51/28
[16:20:08.380]     INFO: ROC 0 masking pixel 51/29
[16:20:08.380]     INFO: ROC 0 masking pixel 51/30
[16:20:08.380]     INFO: ROC 0 masking pixel 51/31
[16:20:08.380]     INFO: ROC 0 masking pixel 51/32
[16:20:08.380]     INFO: ROC 0 masking pixel 51/33
[16:20:08.380]     INFO: ROC 0 masking pixel 51/34
[16:20:08.380]     INFO: ROC 0 masking pixel 51/35
[16:20:08.380]     INFO: ROC 0 masking pixel 51/36
[16:20:08.380]     INFO: ROC 0 masking pixel 51/37
[16:20:08.380]     INFO: ROC 0 masking pixel 51/38
[16:20:08.380]     INFO: ROC 0 masking pixel 51/39
[16:20:08.380]     INFO: ROC 0 masking pixel 51/40
[16:20:08.380]     INFO: ROC 0 masking pixel 51/41
[16:20:08.380]     INFO: ROC 0 masking pixel 51/42
[16:20:08.380]     INFO: ROC 0 masking pixel 51/43
[16:20:08.380]     INFO: ROC 0 masking pixel 51/44
[16:20:08.380]     INFO: ROC 0 masking pixel 51/45
[16:20:08.380]     INFO: ROC 0 masking pixel 51/46
[16:20:08.380]     INFO: ROC 0 masking pixel 51/47
[16:20:08.380]     INFO: ROC 0 masking pixel 51/48
[16:20:08.380]     INFO: ROC 0 masking pixel 51/49
[16:20:08.380]     INFO: ROC 0 masking pixel 51/50
[16:20:08.380]     INFO: ROC 0 masking pixel 51/51
[16:20:08.380]     INFO: ROC 0 masking pixel 51/56
[16:20:08.380]     INFO: ROC 0 masking pixel 51/57
[16:20:08.380]     INFO: ROC 0 masking pixel 51/58
[16:20:08.380]     INFO: ROC 0 masking pixel 51/60
[16:20:08.380]     INFO: ROC 0 masking pixel 51/61
[16:20:08.380]     INFO: ROC 0 masking pixel 51/62
[16:20:08.380]     INFO: ROC 1 masking pixel 29/10
[16:20:08.380]     INFO: ROC 1 masking pixel 29/11
[16:20:08.381]     INFO: ROC 1 masking pixel 29/12
[16:20:08.381]     INFO: ROC 1 masking pixel 29/13
[16:20:08.381]     INFO: ROC 1 masking pixel 29/14
[16:20:08.381]     INFO: ROC 1 masking pixel 30/9
[16:20:08.381]     INFO: ROC 1 masking pixel 30/10
[16:20:08.381]     INFO: ROC 1 masking pixel 30/11
[16:20:08.381]     INFO: ROC 1 masking pixel 30/12
[16:20:08.381]     INFO: ROC 1 masking pixel 30/13
[16:20:08.381]     INFO: ROC 1 masking pixel 30/14
[16:20:08.381]     INFO: ROC 1 masking pixel 30/15
[16:20:08.381]     INFO: ROC 1 masking pixel 31/8
[16:20:08.381]     INFO: ROC 1 masking pixel 31/9
[16:20:08.381]     INFO: ROC 1 masking pixel 31/10
[16:20:08.381]     INFO: ROC 1 masking pixel 31/11
[16:20:08.381]     INFO: ROC 1 masking pixel 31/12
[16:20:08.381]     INFO: ROC 1 masking pixel 31/13
[16:20:08.381]     INFO: ROC 1 masking pixel 31/14
[16:20:08.381]     INFO: ROC 1 masking pixel 31/15
[16:20:08.381]     INFO: ROC 1 masking pixel 31/16
[16:20:08.381]     INFO: ROC 1 masking pixel 32/9
[16:20:08.381]     INFO: ROC 1 masking pixel 32/10
[16:20:08.381]     INFO: ROC 1 masking pixel 32/11
[16:20:08.381]     INFO: ROC 1 masking pixel 32/12
[16:20:08.381]     INFO: ROC 1 masking pixel 32/13
[16:20:08.381]     INFO: ROC 1 masking pixel 32/14
[16:20:08.381]     INFO: ROC 1 masking pixel 32/15
[16:20:08.381]     INFO: ROC 1 masking pixel 32/16
[16:20:08.381]     INFO: ROC 1 masking pixel 33/10
[16:20:08.381]     INFO: ROC 1 masking pixel 33/11
[16:20:08.381]     INFO: ROC 1 masking pixel 33/12
[16:20:08.381]     INFO: ROC 1 masking pixel 33/13
[16:20:08.381]     INFO: ROC 1 masking pixel 33/14
[16:20:08.381]     INFO: ROC 1 masking pixel 33/15
[16:20:08.381]     INFO: ROC 1 masking pixel 33/26
[16:20:08.381]     INFO: ROC 1 masking pixel 33/27
[16:20:08.381]     INFO: ROC 1 masking pixel 34/9
[16:20:08.381]     INFO: ROC 1 masking pixel 34/10
[16:20:08.381]     INFO: ROC 1 masking pixel 34/11
[16:20:08.381]     INFO: ROC 1 masking pixel 34/12
[16:20:08.381]     INFO: ROC 1 masking pixel 34/13
[16:20:08.381]     INFO: ROC 1 masking pixel 34/26
[16:20:08.381]     INFO: ROC 1 masking pixel 34/27
[16:20:08.381]     INFO: ROC 1 masking pixel 34/28
[16:20:08.381]     INFO: ROC 1 masking pixel 35/9
[16:20:08.381]     INFO: ROC 1 masking pixel 35/10
[16:20:08.381]     INFO: ROC 1 masking pixel 35/11
[16:20:08.381]     INFO: ROC 1 masking pixel 35/12
[16:20:08.381]     INFO: ROC 1 masking pixel 35/13
[16:20:08.381]     INFO: ROC 1 masking pixel 35/14
[16:20:08.381]     INFO: ROC 1 masking pixel 35/15
[16:20:08.382]     INFO: ROC 1 masking pixel 35/16
[16:20:08.382]     INFO: ROC 1 masking pixel 35/25
[16:20:08.382]     INFO: ROC 1 masking pixel 35/26
[16:20:08.382]     INFO: ROC 1 masking pixel 35/27
[16:20:08.382]     INFO: ROC 1 masking pixel 35/28
[16:20:08.382]     INFO: ROC 1 masking pixel 35/29
[16:20:08.382]     INFO: ROC 1 masking pixel 35/37
[16:20:08.382]     INFO: ROC 1 masking pixel 35/38
[16:20:08.382]     INFO: ROC 1 masking pixel 36/27
[16:20:08.382]     INFO: ROC 1 masking pixel 36/38
[16:20:08.382]     INFO: ROC 1 masking pixel 36/40
[16:20:08.382]     INFO: ROC 1 masking pixel 36/42
[16:20:08.382]     INFO: ROC 1 masking pixel 37/41
[16:20:08.382]     INFO: ROC 1 masking pixel 37/42
[16:20:08.382]     INFO: ROC 1 masking pixel 37/43
[16:20:08.382]     INFO: ROC 1 masking pixel 37/48
[16:20:08.382]     INFO: ROC 1 masking pixel 37/49
[16:20:08.382]     INFO: ROC 1 masking pixel 37/53
[16:20:08.382]     INFO: ROC 1 masking pixel 37/54
[16:20:08.382]     INFO: ROC 1 masking pixel 38/48
[16:20:08.382]     INFO: ROC 1 masking pixel 38/49
[16:20:08.382]     INFO: ROC 1 masking pixel 38/50
[16:20:08.382]     INFO: ROC 1 masking pixel 38/51
[16:20:08.382]     INFO: ROC 1 masking pixel 38/52
[16:20:08.382]     INFO: ROC 1 masking pixel 38/53
[16:20:08.382]     INFO: ROC 1 masking pixel 38/54
[16:20:08.382]     INFO: ROC 1 masking pixel 39/51
[16:20:08.382]     INFO: ROC 1 masking pixel 39/52
[16:20:08.382]     INFO: ROC 1 masking pixel 39/53
[16:20:08.382]     INFO: ROC 1 masking pixel 39/54
[16:20:08.382]     INFO: ROC 1 masking pixel 39/55
[16:20:08.382]     INFO: ROC 1 masking pixel 39/56
[16:20:08.382]     INFO: ROC 1 masking pixel 39/57
[16:20:08.382]     INFO: ROC 1 masking pixel 39/58
[16:20:08.382]     INFO: ROC 1 masking pixel 40/53
[16:20:08.382]     INFO: ROC 1 masking pixel 40/57
[16:20:08.382]     INFO: ROC 1 masking pixel 40/58
[16:20:08.382]     INFO: ROC 1 masking pixel 40/59
[16:20:08.382]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:08.760]     INFO: Expecting 41600 events.
[16:20:13.178]     INFO: 41600 events read in total (3700ms).
[16:20:13.326]     INFO: Test took 4944ms.
[16:20:13.338]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:13.338]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66405
[16:20:13.338]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists PixelAlive_C0 .. PixelAlive_C15
[16:20:13.619]     INFO: PixTestAlive::aliveTest() done
[16:20:13.619]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:20:13.619]    DEBUG: <PixTestAlive.cc/aliveTest:L199> number of red-efficiency pixels:    83   94   19   27   34   31   33   32   43   33   35   35   35   23   16   19
[16:20:13.620]     INFO: ROC 0 masking pixel 50/5
[16:20:13.620]     INFO: ROC 0 masking pixel 50/6
[16:20:13.620]     INFO: ROC 0 masking pixel 50/7
[16:20:13.620]     INFO: ROC 0 masking pixel 50/8
[16:20:13.620]     INFO: ROC 0 masking pixel 50/9
[16:20:13.620]     INFO: ROC 0 masking pixel 50/10
[16:20:13.620]     INFO: ROC 0 masking pixel 50/11
[16:20:13.620]     INFO: ROC 0 masking pixel 50/12
[16:20:13.620]     INFO: ROC 0 masking pixel 50/13
[16:20:13.620]     INFO: ROC 0 masking pixel 50/15
[16:20:13.620]     INFO: ROC 0 masking pixel 51/3
[16:20:13.620]     INFO: ROC 0 masking pixel 51/4
[16:20:13.620]     INFO: ROC 0 masking pixel 51/5
[16:20:13.620]     INFO: ROC 0 masking pixel 51/6
[16:20:13.620]     INFO: ROC 0 masking pixel 51/7
[16:20:13.620]     INFO: ROC 0 masking pixel 51/8
[16:20:13.620]     INFO: ROC 0 masking pixel 51/9
[16:20:13.620]     INFO: ROC 0 masking pixel 51/10
[16:20:13.620]     INFO: ROC 0 masking pixel 51/11
[16:20:13.620]     INFO: ROC 0 masking pixel 51/12
[16:20:13.620]     INFO: ROC 0 masking pixel 51/13
[16:20:13.620]     INFO: ROC 0 masking pixel 51/14
[16:20:13.620]     INFO: ROC 0 masking pixel 51/15
[16:20:13.620]     INFO: ROC 0 masking pixel 51/16
[16:20:13.620]     INFO: ROC 0 masking pixel 51/17
[16:20:13.620]     INFO: ROC 0 masking pixel 51/18
[16:20:13.620]     INFO: ROC 0 masking pixel 51/19
[16:20:13.620]     INFO: ROC 0 masking pixel 51/20
[16:20:13.620]     INFO: ROC 0 masking pixel 51/21
[16:20:13.620]     INFO: ROC 0 masking pixel 51/22
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[16:20:13.620]     INFO: ROC 0 masking pixel 51/25
[16:20:13.620]     INFO: ROC 0 masking pixel 51/26
[16:20:13.620]     INFO: ROC 0 masking pixel 51/27
[16:20:13.620]     INFO: ROC 0 masking pixel 51/28
[16:20:13.620]     INFO: ROC 0 masking pixel 51/29
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[16:20:13.620]     INFO: ROC 0 masking pixel 51/31
[16:20:13.621]     INFO: ROC 0 masking pixel 51/32
[16:20:13.621]     INFO: ROC 0 masking pixel 51/33
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[16:20:13.621]     INFO: ROC 0 masking pixel 51/35
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[16:20:13.621]     INFO: ROC 0 masking pixel 51/37
[16:20:13.621]     INFO: ROC 0 masking pixel 51/38
[16:20:13.621]     INFO: ROC 0 masking pixel 51/39
[16:20:13.621]     INFO: ROC 0 masking pixel 51/40
[16:20:13.621]     INFO: ROC 0 masking pixel 51/41
[16:20:13.621]     INFO: ROC 0 masking pixel 51/42
[16:20:13.621]     INFO: ROC 0 masking pixel 51/43
[16:20:13.621]     INFO: ROC 0 masking pixel 51/44
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[16:20:13.621]     INFO: ROC 0 masking pixel 51/46
[16:20:13.621]     INFO: ROC 0 masking pixel 51/47
[16:20:13.621]     INFO: ROC 0 masking pixel 51/48
[16:20:13.621]     INFO: ROC 0 masking pixel 51/49
[16:20:13.621]     INFO: ROC 0 masking pixel 51/50
[16:20:13.621]     INFO: ROC 0 masking pixel 51/51
[16:20:13.621]     INFO: ROC 0 masking pixel 51/56
[16:20:13.621]     INFO: ROC 0 masking pixel 51/57
[16:20:13.621]     INFO: ROC 0 masking pixel 51/58
[16:20:13.621]     INFO: ROC 0 masking pixel 51/60
[16:20:13.621]     INFO: ROC 0 masking pixel 51/61
[16:20:13.621]     INFO: ROC 0 masking pixel 51/62
[16:20:13.621]     INFO: ROC 1 masking pixel 29/10
[16:20:13.621]     INFO: ROC 1 masking pixel 29/11
[16:20:13.621]     INFO: ROC 1 masking pixel 29/12
[16:20:13.621]     INFO: ROC 1 masking pixel 29/13
[16:20:13.621]     INFO: ROC 1 masking pixel 29/14
[16:20:13.621]     INFO: ROC 1 masking pixel 30/9
[16:20:13.621]     INFO: ROC 1 masking pixel 30/10
[16:20:13.621]     INFO: ROC 1 masking pixel 30/11
[16:20:13.621]     INFO: ROC 1 masking pixel 30/12
[16:20:13.621]     INFO: ROC 1 masking pixel 30/13
[16:20:13.621]     INFO: ROC 1 masking pixel 30/14
[16:20:13.621]     INFO: ROC 1 masking pixel 30/15
[16:20:13.621]     INFO: ROC 1 masking pixel 31/8
[16:20:13.621]     INFO: ROC 1 masking pixel 31/9
[16:20:13.621]     INFO: ROC 1 masking pixel 31/10
[16:20:13.621]     INFO: ROC 1 masking pixel 31/11
[16:20:13.621]     INFO: ROC 1 masking pixel 31/12
[16:20:13.621]     INFO: ROC 1 masking pixel 31/13
[16:20:13.621]     INFO: ROC 1 masking pixel 31/14
[16:20:13.621]     INFO: ROC 1 masking pixel 31/15
[16:20:13.621]     INFO: ROC 1 masking pixel 31/16
[16:20:13.621]     INFO: ROC 1 masking pixel 32/9
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[16:20:13.621]     INFO: ROC 1 masking pixel 32/11
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[16:20:13.622]     INFO: ROC 1 masking pixel 32/13
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[16:20:13.622]     INFO: ROC 1 masking pixel 33/10
[16:20:13.622]     INFO: ROC 1 masking pixel 33/11
[16:20:13.622]     INFO: ROC 1 masking pixel 33/12
[16:20:13.622]     INFO: ROC 1 masking pixel 33/13
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[16:20:13.622]     INFO: ROC 1 masking pixel 33/15
[16:20:13.622]     INFO: ROC 1 masking pixel 33/26
[16:20:13.622]     INFO: ROC 1 masking pixel 33/27
[16:20:13.622]     INFO: ROC 1 masking pixel 34/9
[16:20:13.622]     INFO: ROC 1 masking pixel 34/10
[16:20:13.622]     INFO: ROC 1 masking pixel 34/11
[16:20:13.622]     INFO: ROC 1 masking pixel 34/12
[16:20:13.622]     INFO: ROC 1 masking pixel 34/13
[16:20:13.622]     INFO: ROC 1 masking pixel 34/26
[16:20:13.622]     INFO: ROC 1 masking pixel 34/27
[16:20:13.622]     INFO: ROC 1 masking pixel 34/28
[16:20:13.622]     INFO: ROC 1 masking pixel 35/9
[16:20:13.622]     INFO: ROC 1 masking pixel 35/10
[16:20:13.622]     INFO: ROC 1 masking pixel 35/11
[16:20:13.622]     INFO: ROC 1 masking pixel 35/12
[16:20:13.622]     INFO: ROC 1 masking pixel 35/13
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[16:20:13.622]     INFO: ROC 1 masking pixel 35/15
[16:20:13.622]     INFO: ROC 1 masking pixel 35/16
[16:20:13.622]     INFO: ROC 1 masking pixel 35/25
[16:20:13.622]     INFO: ROC 1 masking pixel 35/26
[16:20:13.622]     INFO: ROC 1 masking pixel 35/27
[16:20:13.622]     INFO: ROC 1 masking pixel 35/28
[16:20:13.622]     INFO: ROC 1 masking pixel 35/29
[16:20:13.622]     INFO: ROC 1 masking pixel 35/37
[16:20:13.622]     INFO: ROC 1 masking pixel 35/38
[16:20:13.622]     INFO: ROC 1 masking pixel 36/27
[16:20:13.622]     INFO: ROC 1 masking pixel 36/38
[16:20:13.622]     INFO: ROC 1 masking pixel 36/40
[16:20:13.622]     INFO: ROC 1 masking pixel 36/42
[16:20:13.622]     INFO: ROC 1 masking pixel 37/41
[16:20:13.622]     INFO: ROC 1 masking pixel 37/42
[16:20:13.622]     INFO: ROC 1 masking pixel 37/43
[16:20:13.622]     INFO: ROC 1 masking pixel 37/48
[16:20:13.622]     INFO: ROC 1 masking pixel 37/49
[16:20:13.622]     INFO: ROC 1 masking pixel 37/53
[16:20:13.622]     INFO: ROC 1 masking pixel 37/54
[16:20:13.622]     INFO: ROC 1 masking pixel 38/48
[16:20:13.622]     INFO: ROC 1 masking pixel 38/49
[16:20:13.622]     INFO: ROC 1 masking pixel 38/50
[16:20:13.622]     INFO: ROC 1 masking pixel 38/51
[16:20:13.622]     INFO: ROC 1 masking pixel 38/52
[16:20:13.622]     INFO: ROC 1 masking pixel 38/53
[16:20:13.622]     INFO: ROC 1 masking pixel 38/54
[16:20:13.622]     INFO: ROC 1 masking pixel 39/51
[16:20:13.622]     INFO: ROC 1 masking pixel 39/52
[16:20:13.622]     INFO: ROC 1 masking pixel 39/53
[16:20:13.622]     INFO: ROC 1 masking pixel 39/54
[16:20:13.622]     INFO: ROC 1 masking pixel 39/55
[16:20:13.622]     INFO: ROC 1 masking pixel 39/56
[16:20:13.622]     INFO: ROC 1 masking pixel 39/57
[16:20:13.622]     INFO: ROC 1 masking pixel 39/58
[16:20:13.622]     INFO: ROC 1 masking pixel 40/53
[16:20:13.622]     INFO: ROC 1 masking pixel 40/57
[16:20:13.622]     INFO: ROC 1 masking pixel 40/58
[16:20:13.622]     INFO: ROC 1 masking pixel 40/59
[16:20:13.647]     INFO:    ----------------------------------------------------------------------
[16:20:13.647]     INFO:    PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:20:13.647]     INFO:    ----------------------------------------------------------------------
[16:20:13.652]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:14.031]     INFO: Expecting 41600 events.
[16:20:17.150]     INFO: 41600 events read in total (2404ms).
[16:20:17.151]     INFO: Test took 3499ms.
[16:20:17.151]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:17.151]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 0
[16:20:17.151]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists MaskTest_C0 .. MaskTest_C15
[16:20:17.151]     INFO: ROC 0 masking pixel 50/5
[16:20:17.151]     INFO: ROC 0 masking pixel 50/6
[16:20:17.151]     INFO: ROC 0 masking pixel 50/7
[16:20:17.151]     INFO: ROC 0 masking pixel 50/8
[16:20:17.151]     INFO: ROC 0 masking pixel 50/9
[16:20:17.151]     INFO: ROC 0 masking pixel 50/10
[16:20:17.151]     INFO: ROC 0 masking pixel 50/11
[16:20:17.151]     INFO: ROC 0 masking pixel 50/12
[16:20:17.151]     INFO: ROC 0 masking pixel 50/13
[16:20:17.151]     INFO: ROC 0 masking pixel 50/15
[16:20:17.151]     INFO: ROC 0 masking pixel 51/3
[16:20:17.151]     INFO: ROC 0 masking pixel 51/4
[16:20:17.152]     INFO: ROC 0 masking pixel 51/5
[16:20:17.152]     INFO: ROC 0 masking pixel 51/6
[16:20:17.152]     INFO: ROC 0 masking pixel 51/7
[16:20:17.152]     INFO: ROC 0 masking pixel 51/8
[16:20:17.152]     INFO: ROC 0 masking pixel 51/9
[16:20:17.152]     INFO: ROC 0 masking pixel 51/10
[16:20:17.152]     INFO: ROC 0 masking pixel 51/11
[16:20:17.152]     INFO: ROC 0 masking pixel 51/12
[16:20:17.152]     INFO: ROC 0 masking pixel 51/13
[16:20:17.152]     INFO: ROC 0 masking pixel 51/14
[16:20:17.152]     INFO: ROC 0 masking pixel 51/15
[16:20:17.152]     INFO: ROC 0 masking pixel 51/16
[16:20:17.152]     INFO: ROC 0 masking pixel 51/17
[16:20:17.152]     INFO: ROC 0 masking pixel 51/18
[16:20:17.152]     INFO: ROC 0 masking pixel 51/19
[16:20:17.152]     INFO: ROC 0 masking pixel 51/20
[16:20:17.152]     INFO: ROC 0 masking pixel 51/21
[16:20:17.152]     INFO: ROC 0 masking pixel 51/22
[16:20:17.152]     INFO: ROC 0 masking pixel 51/23
[16:20:17.152]     INFO: ROC 0 masking pixel 51/24
[16:20:17.152]     INFO: ROC 0 masking pixel 51/25
[16:20:17.152]     INFO: ROC 0 masking pixel 51/26
[16:20:17.152]     INFO: ROC 0 masking pixel 51/27
[16:20:17.152]     INFO: ROC 0 masking pixel 51/28
[16:20:17.152]     INFO: ROC 0 masking pixel 51/29
[16:20:17.152]     INFO: ROC 0 masking pixel 51/30
[16:20:17.152]     INFO: ROC 0 masking pixel 51/31
[16:20:17.152]     INFO: ROC 0 masking pixel 51/32
[16:20:17.152]     INFO: ROC 0 masking pixel 51/33
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[16:20:17.152]     INFO: ROC 0 masking pixel 51/35
[16:20:17.152]     INFO: ROC 0 masking pixel 51/36
[16:20:17.152]     INFO: ROC 0 masking pixel 51/37
[16:20:17.152]     INFO: ROC 0 masking pixel 51/38
[16:20:17.152]     INFO: ROC 0 masking pixel 51/39
[16:20:17.152]     INFO: ROC 0 masking pixel 51/40
[16:20:17.152]     INFO: ROC 0 masking pixel 51/41
[16:20:17.152]     INFO: ROC 0 masking pixel 51/42
[16:20:17.152]     INFO: ROC 0 masking pixel 51/43
[16:20:17.152]     INFO: ROC 0 masking pixel 51/44
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[16:20:17.152]     INFO: ROC 0 masking pixel 51/46
[16:20:17.152]     INFO: ROC 0 masking pixel 51/47
[16:20:17.152]     INFO: ROC 0 masking pixel 51/48
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[16:20:17.152]     INFO: ROC 0 masking pixel 51/50
[16:20:17.153]     INFO: ROC 0 masking pixel 51/51
[16:20:17.153]     INFO: ROC 0 masking pixel 51/56
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[16:20:17.153]     INFO: ROC 0 masking pixel 51/58
[16:20:17.153]     INFO: ROC 0 masking pixel 51/60
[16:20:17.153]     INFO: ROC 0 masking pixel 51/61
[16:20:17.153]     INFO: ROC 0 masking pixel 51/62
[16:20:17.153]     INFO: ROC 1 masking pixel 29/10
[16:20:17.153]     INFO: ROC 1 masking pixel 29/11
[16:20:17.153]     INFO: ROC 1 masking pixel 29/12
[16:20:17.153]     INFO: ROC 1 masking pixel 29/13
[16:20:17.153]     INFO: ROC 1 masking pixel 29/14
[16:20:17.153]     INFO: ROC 1 masking pixel 30/9
[16:20:17.153]     INFO: ROC 1 masking pixel 30/10
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[16:20:17.153]     INFO: ROC 1 masking pixel 31/8
[16:20:17.153]     INFO: ROC 1 masking pixel 31/9
[16:20:17.153]     INFO: ROC 1 masking pixel 31/10
[16:20:17.153]     INFO: ROC 1 masking pixel 31/11
[16:20:17.153]     INFO: ROC 1 masking pixel 31/12
[16:20:17.153]     INFO: ROC 1 masking pixel 31/13
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[16:20:17.153]     INFO: ROC 1 masking pixel 31/15
[16:20:17.153]     INFO: ROC 1 masking pixel 31/16
[16:20:17.153]     INFO: ROC 1 masking pixel 32/9
[16:20:17.153]     INFO: ROC 1 masking pixel 32/10
[16:20:17.153]     INFO: ROC 1 masking pixel 32/11
[16:20:17.153]     INFO: ROC 1 masking pixel 32/12
[16:20:17.153]     INFO: ROC 1 masking pixel 32/13
[16:20:17.153]     INFO: ROC 1 masking pixel 32/14
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[16:20:17.153]     INFO: ROC 1 masking pixel 32/16
[16:20:17.153]     INFO: ROC 1 masking pixel 33/10
[16:20:17.153]     INFO: ROC 1 masking pixel 33/11
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[16:20:17.153]     INFO: ROC 1 masking pixel 33/13
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[16:20:17.153]     INFO: ROC 1 masking pixel 33/27
[16:20:17.153]     INFO: ROC 1 masking pixel 34/9
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[16:20:17.153]     INFO: ROC 1 masking pixel 34/11
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[16:20:17.153]     INFO: ROC 1 masking pixel 34/27
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[16:20:17.153]     INFO: ROC 1 masking pixel 35/9
[16:20:17.153]     INFO: ROC 1 masking pixel 35/10
[16:20:17.153]     INFO: ROC 1 masking pixel 35/11
[16:20:17.153]     INFO: ROC 1 masking pixel 35/12
[16:20:17.153]     INFO: ROC 1 masking pixel 35/13
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[16:20:17.153]     INFO: ROC 1 masking pixel 35/15
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[16:20:17.153]     INFO: ROC 1 masking pixel 35/25
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[16:20:17.153]     INFO: ROC 1 masking pixel 35/27
[16:20:17.153]     INFO: ROC 1 masking pixel 35/28
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[16:20:17.154]     INFO: ROC 1 masking pixel 35/37
[16:20:17.154]     INFO: ROC 1 masking pixel 35/38
[16:20:17.154]     INFO: ROC 1 masking pixel 36/27
[16:20:17.154]     INFO: ROC 1 masking pixel 36/38
[16:20:17.154]     INFO: ROC 1 masking pixel 36/40
[16:20:17.154]     INFO: ROC 1 masking pixel 36/42
[16:20:17.154]     INFO: ROC 1 masking pixel 37/41
[16:20:17.154]     INFO: ROC 1 masking pixel 37/42
[16:20:17.154]     INFO: ROC 1 masking pixel 37/43
[16:20:17.154]     INFO: ROC 1 masking pixel 37/48
[16:20:17.154]     INFO: ROC 1 masking pixel 37/49
[16:20:17.154]     INFO: ROC 1 masking pixel 37/53
[16:20:17.154]     INFO: ROC 1 masking pixel 37/54
[16:20:17.154]     INFO: ROC 1 masking pixel 38/48
[16:20:17.154]     INFO: ROC 1 masking pixel 38/49
[16:20:17.154]     INFO: ROC 1 masking pixel 38/50
[16:20:17.154]     INFO: ROC 1 masking pixel 38/51
[16:20:17.154]     INFO: ROC 1 masking pixel 38/52
[16:20:17.154]     INFO: ROC 1 masking pixel 38/53
[16:20:17.154]     INFO: ROC 1 masking pixel 38/54
[16:20:17.154]     INFO: ROC 1 masking pixel 39/51
[16:20:17.154]     INFO: ROC 1 masking pixel 39/52
[16:20:17.154]     INFO: ROC 1 masking pixel 39/53
[16:20:17.154]     INFO: ROC 1 masking pixel 39/54
[16:20:17.154]     INFO: ROC 1 masking pixel 39/55
[16:20:17.154]     INFO: ROC 1 masking pixel 39/56
[16:20:17.154]     INFO: ROC 1 masking pixel 39/57
[16:20:17.154]     INFO: ROC 1 masking pixel 39/58
[16:20:17.154]     INFO: ROC 1 masking pixel 40/53
[16:20:17.154]     INFO: ROC 1 masking pixel 40/57
[16:20:17.154]     INFO: ROC 1 masking pixel 40/58
[16:20:17.154]     INFO: ROC 1 masking pixel 40/59
[16:20:17.154]     INFO: mask vs. old pixelAlive PixelAlive_C0_V0 ..  PixelAlive_C15_V0
[16:20:17.574]     INFO: PixTestAlive::maskTest() done
[16:20:17.574]     INFO: number of mask-defect pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:20:17.574]     INFO: ROC 0 masking pixel 50/5
[16:20:17.574]     INFO: ROC 0 masking pixel 50/6
[16:20:17.574]     INFO: ROC 0 masking pixel 50/7
[16:20:17.574]     INFO: ROC 0 masking pixel 50/8
[16:20:17.574]     INFO: ROC 0 masking pixel 50/9
[16:20:17.574]     INFO: ROC 0 masking pixel 50/10
[16:20:17.574]     INFO: ROC 0 masking pixel 50/11
[16:20:17.574]     INFO: ROC 0 masking pixel 50/12
[16:20:17.574]     INFO: ROC 0 masking pixel 50/13
[16:20:17.574]     INFO: ROC 0 masking pixel 50/15
[16:20:17.574]     INFO: ROC 0 masking pixel 51/3
[16:20:17.574]     INFO: ROC 0 masking pixel 51/4
[16:20:17.574]     INFO: ROC 0 masking pixel 51/5
[16:20:17.574]     INFO: ROC 0 masking pixel 51/6
[16:20:17.574]     INFO: ROC 0 masking pixel 51/7
[16:20:17.574]     INFO: ROC 0 masking pixel 51/8
[16:20:17.574]     INFO: ROC 0 masking pixel 51/9
[16:20:17.574]     INFO: ROC 0 masking pixel 51/10
[16:20:17.574]     INFO: ROC 0 masking pixel 51/11
[16:20:17.574]     INFO: ROC 0 masking pixel 51/12
[16:20:17.574]     INFO: ROC 0 masking pixel 51/13
[16:20:17.574]     INFO: ROC 0 masking pixel 51/14
[16:20:17.574]     INFO: ROC 0 masking pixel 51/15
[16:20:17.574]     INFO: ROC 0 masking pixel 51/16
[16:20:17.574]     INFO: ROC 0 masking pixel 51/17
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[16:20:17.600]     INFO:    ----------------------------------------------------------------------
[16:20:17.600]     INFO:    PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:20:17.600]     INFO:    ----------------------------------------------------------------------
[16:20:17.604]     INFO: ROC 0 masking pixel 50/5
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[16:20:17.607]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:17.985]     INFO: Expecting 41600 events.
[16:20:22.405]     INFO: 41600 events read in total (3705ms).
[16:20:22.407]     INFO: Test took 4800ms.
[16:20:22.416]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:22.416]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66405
[16:20:22.416]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists AddressDecodingTest_C0 .. AddressDecodingTest_C15
[16:20:22.786]     INFO: PixTestAlive::addressDecodingTest() done
[16:20:22.786]     INFO: number of address-decoding pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:20:22.787]     INFO: ROC 0 masking pixel 50/5
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[16:20:22.788]     INFO: ROC 1 masking pixel 31/14
[16:20:22.788]     INFO: ROC 1 masking pixel 31/15
[16:20:22.788]     INFO: ROC 1 masking pixel 31/16
[16:20:22.788]     INFO: ROC 1 masking pixel 32/9
[16:20:22.788]     INFO: ROC 1 masking pixel 32/10
[16:20:22.788]     INFO: ROC 1 masking pixel 32/11
[16:20:22.788]     INFO: ROC 1 masking pixel 32/12
[16:20:22.788]     INFO: ROC 1 masking pixel 32/13
[16:20:22.788]     INFO: ROC 1 masking pixel 32/14
[16:20:22.789]     INFO: ROC 1 masking pixel 32/15
[16:20:22.789]     INFO: ROC 1 masking pixel 32/16
[16:20:22.789]     INFO: ROC 1 masking pixel 33/10
[16:20:22.789]     INFO: ROC 1 masking pixel 33/11
[16:20:22.789]     INFO: ROC 1 masking pixel 33/12
[16:20:22.789]     INFO: ROC 1 masking pixel 33/13
[16:20:22.789]     INFO: ROC 1 masking pixel 33/14
[16:20:22.789]     INFO: ROC 1 masking pixel 33/15
[16:20:22.789]     INFO: ROC 1 masking pixel 33/26
[16:20:22.789]     INFO: ROC 1 masking pixel 33/27
[16:20:22.789]     INFO: ROC 1 masking pixel 34/9
[16:20:22.789]     INFO: ROC 1 masking pixel 34/10
[16:20:22.789]     INFO: ROC 1 masking pixel 34/11
[16:20:22.789]     INFO: ROC 1 masking pixel 34/12
[16:20:22.789]     INFO: ROC 1 masking pixel 34/13
[16:20:22.789]     INFO: ROC 1 masking pixel 34/26
[16:20:22.789]     INFO: ROC 1 masking pixel 34/27
[16:20:22.789]     INFO: ROC 1 masking pixel 34/28
[16:20:22.789]     INFO: ROC 1 masking pixel 35/9
[16:20:22.789]     INFO: ROC 1 masking pixel 35/10
[16:20:22.789]     INFO: ROC 1 masking pixel 35/11
[16:20:22.789]     INFO: ROC 1 masking pixel 35/12
[16:20:22.789]     INFO: ROC 1 masking pixel 35/13
[16:20:22.789]     INFO: ROC 1 masking pixel 35/14
[16:20:22.789]     INFO: ROC 1 masking pixel 35/15
[16:20:22.789]     INFO: ROC 1 masking pixel 35/16
[16:20:22.789]     INFO: ROC 1 masking pixel 35/25
[16:20:22.789]     INFO: ROC 1 masking pixel 35/26
[16:20:22.789]     INFO: ROC 1 masking pixel 35/27
[16:20:22.789]     INFO: ROC 1 masking pixel 35/28
[16:20:22.789]     INFO: ROC 1 masking pixel 35/29
[16:20:22.789]     INFO: ROC 1 masking pixel 35/37
[16:20:22.789]     INFO: ROC 1 masking pixel 35/38
[16:20:22.789]     INFO: ROC 1 masking pixel 36/27
[16:20:22.789]     INFO: ROC 1 masking pixel 36/38
[16:20:22.789]     INFO: ROC 1 masking pixel 36/40
[16:20:22.789]     INFO: ROC 1 masking pixel 36/42
[16:20:22.789]     INFO: ROC 1 masking pixel 37/41
[16:20:22.789]     INFO: ROC 1 masking pixel 37/42
[16:20:22.789]     INFO: ROC 1 masking pixel 37/43
[16:20:22.789]     INFO: ROC 1 masking pixel 37/48
[16:20:22.789]     INFO: ROC 1 masking pixel 37/49
[16:20:22.789]     INFO: ROC 1 masking pixel 37/53
[16:20:22.789]     INFO: ROC 1 masking pixel 37/54
[16:20:22.789]     INFO: ROC 1 masking pixel 38/48
[16:20:22.789]     INFO: ROC 1 masking pixel 38/49
[16:20:22.789]     INFO: ROC 1 masking pixel 38/50
[16:20:22.789]     INFO: ROC 1 masking pixel 38/51
[16:20:22.790]     INFO: ROC 1 masking pixel 38/52
[16:20:22.790]     INFO: ROC 1 masking pixel 38/53
[16:20:22.790]     INFO: ROC 1 masking pixel 38/54
[16:20:22.790]     INFO: ROC 1 masking pixel 39/51
[16:20:22.790]     INFO: ROC 1 masking pixel 39/52
[16:20:22.790]     INFO: ROC 1 masking pixel 39/53
[16:20:22.790]     INFO: ROC 1 masking pixel 39/54
[16:20:22.790]     INFO: ROC 1 masking pixel 39/55
[16:20:22.790]     INFO: ROC 1 masking pixel 39/56
[16:20:22.790]     INFO: ROC 1 masking pixel 39/57
[16:20:22.790]     INFO: ROC 1 masking pixel 39/58
[16:20:22.790]     INFO: ROC 1 masking pixel 40/53
[16:20:22.790]     INFO: ROC 1 masking pixel 40/57
[16:20:22.790]     INFO: ROC 1 masking pixel 40/58
[16:20:22.790]     INFO: ROC 1 masking pixel 40/59
[16:20:22.790]     INFO: PixTestAlive::doTest() done, duration: 14 seconds
[16:20:34.410]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  caldelscan
[16:20:34.410]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: caldelscan
[16:20:34.410]     INFO:    ----------------------------------------------------------------------
[16:20:34.410]     INFO:    PixTestHighRate::calDelScan() ntrig = 10, vcal = 200
[16:20:34.410]     INFO:    ----------------------------------------------------------------------
[16:20:34.549]     INFO: Expecting 768 events.
[16:20:35.683]     INFO: 768 events read in total (419ms).
[16:20:35.683]     INFO: Test took 1267ms.
[16:20:35.686]     INFO: ROC 0 masking pixel 50/5
[16:20:35.686]     INFO: ROC 0 masking pixel 50/6
[16:20:35.686]     INFO: ROC 0 masking pixel 50/7
[16:20:35.686]     INFO: ROC 0 masking pixel 50/8
[16:20:35.686]     INFO: ROC 0 masking pixel 50/9
[16:20:35.686]     INFO: ROC 0 masking pixel 50/10
[16:20:35.686]     INFO: ROC 0 masking pixel 50/11
[16:20:35.686]     INFO: ROC 0 masking pixel 50/12
[16:20:35.686]     INFO: ROC 0 masking pixel 50/13
[16:20:35.686]     INFO: ROC 0 masking pixel 50/15
[16:20:35.686]     INFO: ROC 0 masking pixel 51/3
[16:20:35.686]     INFO: ROC 0 masking pixel 51/4
[16:20:35.686]     INFO: ROC 0 masking pixel 51/5
[16:20:35.686]     INFO: ROC 0 masking pixel 51/6
[16:20:35.686]     INFO: ROC 0 masking pixel 51/7
[16:20:35.687]     INFO: ROC 0 masking pixel 51/8
[16:20:35.687]     INFO: ROC 0 masking pixel 51/9
[16:20:35.687]     INFO: ROC 0 masking pixel 51/10
[16:20:35.687]     INFO: ROC 0 masking pixel 51/11
[16:20:35.687]     INFO: ROC 0 masking pixel 51/12
[16:20:35.687]     INFO: ROC 0 masking pixel 51/13
[16:20:35.687]     INFO: ROC 0 masking pixel 51/14
[16:20:35.687]     INFO: ROC 0 masking pixel 51/15
[16:20:35.687]     INFO: ROC 0 masking pixel 51/16
[16:20:35.687]     INFO: ROC 0 masking pixel 51/17
[16:20:35.687]     INFO: ROC 0 masking pixel 51/18
[16:20:35.687]     INFO: ROC 0 masking pixel 51/19
[16:20:35.687]     INFO: ROC 0 masking pixel 51/20
[16:20:35.687]     INFO: ROC 0 masking pixel 51/21
[16:20:35.687]     INFO: ROC 0 masking pixel 51/22
[16:20:35.687]     INFO: ROC 0 masking pixel 51/23
[16:20:35.687]     INFO: ROC 0 masking pixel 51/24
[16:20:35.687]     INFO: ROC 0 masking pixel 51/25
[16:20:35.687]     INFO: ROC 0 masking pixel 51/26
[16:20:35.687]     INFO: ROC 0 masking pixel 51/27
[16:20:35.687]     INFO: ROC 0 masking pixel 51/28
[16:20:35.687]     INFO: ROC 0 masking pixel 51/29
[16:20:35.687]     INFO: ROC 0 masking pixel 51/30
[16:20:35.687]     INFO: ROC 0 masking pixel 51/31
[16:20:35.687]     INFO: ROC 0 masking pixel 51/32
[16:20:35.687]     INFO: ROC 0 masking pixel 51/33
[16:20:35.687]     INFO: ROC 0 masking pixel 51/34
[16:20:35.687]     INFO: ROC 0 masking pixel 51/35
[16:20:35.687]     INFO: ROC 0 masking pixel 51/36
[16:20:35.687]     INFO: ROC 0 masking pixel 51/37
[16:20:35.687]     INFO: ROC 0 masking pixel 51/38
[16:20:35.687]     INFO: ROC 0 masking pixel 51/39
[16:20:35.687]     INFO: ROC 0 masking pixel 51/40
[16:20:35.687]     INFO: ROC 0 masking pixel 51/41
[16:20:35.687]     INFO: ROC 0 masking pixel 51/42
[16:20:35.687]     INFO: ROC 0 masking pixel 51/43
[16:20:35.687]     INFO: ROC 0 masking pixel 51/44
[16:20:35.687]     INFO: ROC 0 masking pixel 51/45
[16:20:35.687]     INFO: ROC 0 masking pixel 51/46
[16:20:35.687]     INFO: ROC 0 masking pixel 51/47
[16:20:35.687]     INFO: ROC 0 masking pixel 51/48
[16:20:35.687]     INFO: ROC 0 masking pixel 51/49
[16:20:35.687]     INFO: ROC 0 masking pixel 51/50
[16:20:35.687]     INFO: ROC 0 masking pixel 51/51
[16:20:35.687]     INFO: ROC 0 masking pixel 51/56
[16:20:35.688]     INFO: ROC 0 masking pixel 51/57
[16:20:35.688]     INFO: ROC 0 masking pixel 51/58
[16:20:35.688]     INFO: ROC 0 masking pixel 51/60
[16:20:35.688]     INFO: ROC 0 masking pixel 51/61
[16:20:35.688]     INFO: ROC 0 masking pixel 51/62
[16:20:35.688]     INFO: ROC 1 masking pixel 29/10
[16:20:35.688]     INFO: ROC 1 masking pixel 29/11
[16:20:35.688]     INFO: ROC 1 masking pixel 29/12
[16:20:35.688]     INFO: ROC 1 masking pixel 29/13
[16:20:35.688]     INFO: ROC 1 masking pixel 29/14
[16:20:35.688]     INFO: ROC 1 masking pixel 30/9
[16:20:35.688]     INFO: ROC 1 masking pixel 30/10
[16:20:35.688]     INFO: ROC 1 masking pixel 30/11
[16:20:35.688]     INFO: ROC 1 masking pixel 30/12
[16:20:35.688]     INFO: ROC 1 masking pixel 30/13
[16:20:35.688]     INFO: ROC 1 masking pixel 30/14
[16:20:35.688]     INFO: ROC 1 masking pixel 30/15
[16:20:35.688]     INFO: ROC 1 masking pixel 31/8
[16:20:35.688]     INFO: ROC 1 masking pixel 31/9
[16:20:35.688]     INFO: ROC 1 masking pixel 31/10
[16:20:35.688]     INFO: ROC 1 masking pixel 31/11
[16:20:35.688]     INFO: ROC 1 masking pixel 31/12
[16:20:35.688]     INFO: ROC 1 masking pixel 31/13
[16:20:35.688]     INFO: ROC 1 masking pixel 31/14
[16:20:35.688]     INFO: ROC 1 masking pixel 31/15
[16:20:35.688]     INFO: ROC 1 masking pixel 31/16
[16:20:35.688]     INFO: ROC 1 masking pixel 32/9
[16:20:35.688]     INFO: ROC 1 masking pixel 32/10
[16:20:35.688]     INFO: ROC 1 masking pixel 32/11
[16:20:35.688]     INFO: ROC 1 masking pixel 32/12
[16:20:35.688]     INFO: ROC 1 masking pixel 32/13
[16:20:35.688]     INFO: ROC 1 masking pixel 32/14
[16:20:35.688]     INFO: ROC 1 masking pixel 32/15
[16:20:35.688]     INFO: ROC 1 masking pixel 32/16
[16:20:35.688]     INFO: ROC 1 masking pixel 33/10
[16:20:35.688]     INFO: ROC 1 masking pixel 33/11
[16:20:35.688]     INFO: ROC 1 masking pixel 33/12
[16:20:35.688]     INFO: ROC 1 masking pixel 33/13
[16:20:35.688]     INFO: ROC 1 masking pixel 33/14
[16:20:35.688]     INFO: ROC 1 masking pixel 33/15
[16:20:35.688]     INFO: ROC 1 masking pixel 33/26
[16:20:35.688]     INFO: ROC 1 masking pixel 33/27
[16:20:35.688]     INFO: ROC 1 masking pixel 34/9
[16:20:35.688]     INFO: ROC 1 masking pixel 34/10
[16:20:35.688]     INFO: ROC 1 masking pixel 34/11
[16:20:35.688]     INFO: ROC 1 masking pixel 34/12
[16:20:35.688]     INFO: ROC 1 masking pixel 34/13
[16:20:35.688]     INFO: ROC 1 masking pixel 34/26
[16:20:35.689]     INFO: ROC 1 masking pixel 34/27
[16:20:35.689]     INFO: ROC 1 masking pixel 34/28
[16:20:35.689]     INFO: ROC 1 masking pixel 35/9
[16:20:35.689]     INFO: ROC 1 masking pixel 35/10
[16:20:35.689]     INFO: ROC 1 masking pixel 35/11
[16:20:35.689]     INFO: ROC 1 masking pixel 35/12
[16:20:35.689]     INFO: ROC 1 masking pixel 35/13
[16:20:35.689]     INFO: ROC 1 masking pixel 35/14
[16:20:35.689]     INFO: ROC 1 masking pixel 35/15
[16:20:35.689]     INFO: ROC 1 masking pixel 35/16
[16:20:35.689]     INFO: ROC 1 masking pixel 35/25
[16:20:35.689]     INFO: ROC 1 masking pixel 35/26
[16:20:35.689]     INFO: ROC 1 masking pixel 35/27
[16:20:35.689]     INFO: ROC 1 masking pixel 35/28
[16:20:35.689]     INFO: ROC 1 masking pixel 35/29
[16:20:35.689]     INFO: ROC 1 masking pixel 35/37
[16:20:35.689]     INFO: ROC 1 masking pixel 35/38
[16:20:35.689]     INFO: ROC 1 masking pixel 36/27
[16:20:35.689]     INFO: ROC 1 masking pixel 36/38
[16:20:35.689]     INFO: ROC 1 masking pixel 36/40
[16:20:35.689]     INFO: ROC 1 masking pixel 36/42
[16:20:35.689]     INFO: ROC 1 masking pixel 37/41
[16:20:35.689]     INFO: ROC 1 masking pixel 37/42
[16:20:35.689]     INFO: ROC 1 masking pixel 37/43
[16:20:35.689]     INFO: ROC 1 masking pixel 37/48
[16:20:35.689]     INFO: ROC 1 masking pixel 37/49
[16:20:35.689]     INFO: ROC 1 masking pixel 37/53
[16:20:35.689]     INFO: ROC 1 masking pixel 37/54
[16:20:35.689]     INFO: ROC 1 masking pixel 38/48
[16:20:35.689]     INFO: ROC 1 masking pixel 38/49
[16:20:35.689]     INFO: ROC 1 masking pixel 38/50
[16:20:35.689]     INFO: ROC 1 masking pixel 38/51
[16:20:35.689]     INFO: ROC 1 masking pixel 38/52
[16:20:35.689]     INFO: ROC 1 masking pixel 38/53
[16:20:35.689]     INFO: ROC 1 masking pixel 38/54
[16:20:35.689]     INFO: ROC 1 masking pixel 39/51
[16:20:35.689]     INFO: ROC 1 masking pixel 39/52
[16:20:35.689]     INFO: ROC 1 masking pixel 39/53
[16:20:35.689]     INFO: ROC 1 masking pixel 39/54
[16:20:35.689]     INFO: ROC 1 masking pixel 39/55
[16:20:35.689]     INFO: ROC 1 masking pixel 39/56
[16:20:35.689]     INFO: ROC 1 masking pixel 39/57
[16:20:35.689]     INFO: ROC 1 masking pixel 39/58
[16:20:35.689]     INFO: ROC 1 masking pixel 40/53
[16:20:35.689]     INFO: ROC 1 masking pixel 40/57
[16:20:35.689]     INFO: ROC 1 masking pixel 40/58
[16:20:35.689]     INFO: ROC 1 masking pixel 40/59
[16:20:35.692]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:36.486]     INFO: Expecting 41600 events.
[16:20:39.848]     INFO: 41600 events read in total (2835ms).
[16:20:39.852]     INFO: Test took 4160ms.
[16:20:39.928]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:39.928]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 430467
[16:20:39.928]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step0_C0 .. HR_xeff_CalDelScan_step0_C15
[16:20:39.928]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:20:39.963]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:40.629]     INFO: Expecting 41600 events.
[16:20:44.080]     INFO: 41600 events read in total (2926ms).
[16:20:44.084]     INFO: Test took 4121ms.
[16:20:44.155]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:44.155]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 434556
[16:20:44.155]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step1_C0 .. HR_xeff_CalDelScan_step1_C15
[16:20:44.156]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:20:44.193]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:44.859]     INFO: Expecting 41600 events.
[16:20:48.361]     INFO: 41600 events read in total (2976ms).
[16:20:48.364]     INFO: Test took 4171ms.
[16:20:48.437]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:48.437]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437757
[16:20:48.437]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step2_C0 .. HR_xeff_CalDelScan_step2_C15
[16:20:48.438]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:20:48.475]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:49.140]     INFO: Expecting 41600 events.
[16:20:52.632]     INFO: 41600 events read in total (2965ms).
[16:20:52.636]     INFO: Test took 4161ms.
[16:20:52.709]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:52.709]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 438344
[16:20:52.709]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step3_C0 .. HR_xeff_CalDelScan_step3_C15
[16:20:52.710]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:20:52.747]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:53.413]     INFO: Expecting 41600 events.
[16:20:56.913]     INFO: 41600 events read in total (2973ms).
[16:20:56.917]     INFO: Test took 4170ms.
[16:20:56.990]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:20:56.990]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437595
[16:20:56.990]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step4_C0 .. HR_xeff_CalDelScan_step4_C15
[16:20:56.990]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:20:57.028]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:20:57.693]     INFO: Expecting 41600 events.
[16:21:01.187]     INFO: 41600 events read in total (2967ms).
[16:21:01.191]     INFO: Test took 4163ms.
[16:21:01.270]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:01.270]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437885
[16:21:01.270]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step5_C0 .. HR_xeff_CalDelScan_step5_C15
[16:21:01.270]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:01.309]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:01.979]     INFO: Expecting 41600 events.
[16:21:05.478]     INFO: 41600 events read in total (2973ms).
[16:21:05.482]     INFO: Test took 4173ms.
[16:21:05.554]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:05.554]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 438720
[16:21:05.554]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step6_C0 .. HR_xeff_CalDelScan_step6_C15
[16:21:05.554]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:05.592]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:06.257]     INFO: Expecting 41600 events.
[16:21:09.745]     INFO: 41600 events read in total (2962ms).
[16:21:09.749]     INFO: Test took 4157ms.
[16:21:09.823]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:09.823]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 438232
[16:21:09.823]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step7_C0 .. HR_xeff_CalDelScan_step7_C15
[16:21:09.824]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:09.863]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:10.529]     INFO: Expecting 41600 events.
[16:21:14.035]     INFO: 41600 events read in total (2979ms).
[16:21:14.039]     INFO: Test took 4176ms.
[16:21:14.112]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:14.112]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437499
[16:21:14.112]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step8_C0 .. HR_xeff_CalDelScan_step8_C15
[16:21:14.113]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:14.154]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:14.823]     INFO: Expecting 41600 events.
[16:21:18.312]     INFO: 41600 events read in total (2963ms).
[16:21:18.316]     INFO: Test took 4161ms.
[16:21:18.388]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:18.388]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 438804
[16:21:18.388]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step9_C0 .. HR_xeff_CalDelScan_step9_C15
[16:21:18.388]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:18.426]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:19.090]     INFO: Expecting 41600 events.
[16:21:22.609]     INFO: 41600 events read in total (2992ms).
[16:21:22.612]     INFO: Test took 4186ms.
[16:21:22.684]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:22.684]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437092
[16:21:22.684]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step10_C0 .. HR_xeff_CalDelScan_step10_C15
[16:21:22.685]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:22.722]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:23.387]     INFO: Expecting 41600 events.
[16:21:26.899]     INFO: 41600 events read in total (2985ms).
[16:21:26.903]     INFO: Test took 4181ms.
[16:21:26.975]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:26.975]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 438154
[16:21:26.975]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step11_C0 .. HR_xeff_CalDelScan_step11_C15
[16:21:26.976]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:27.016]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:27.682]     INFO: Expecting 41600 events.
[16:21:31.201]     INFO: 41600 events read in total (2992ms).
[16:21:31.204]     INFO: Test took 4188ms.
[16:21:31.276]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:31.276]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437524
[16:21:31.276]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step12_C0 .. HR_xeff_CalDelScan_step12_C15
[16:21:31.277]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:31.315]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:31.980]     INFO: Expecting 41600 events.
[16:21:35.513]     INFO: 41600 events read in total (3006ms).
[16:21:35.516]     INFO: Test took 4201ms.
[16:21:35.588]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:35.588]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437091
[16:21:35.588]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step13_C0 .. HR_xeff_CalDelScan_step13_C15
[16:21:35.588]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:35.625]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:36.291]     INFO: Expecting 41600 events.
[16:21:39.796]     INFO: 41600 events read in total (2978ms).
[16:21:39.799]     INFO: Test took 4174ms.
[16:21:39.871]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:39.872]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 436815
[16:21:39.872]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step14_C0 .. HR_xeff_CalDelScan_step14_C15
[16:21:39.872]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:39.909]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:40.576]     INFO: Expecting 41600 events.
[16:21:44.075]     INFO: 41600 events read in total (2972ms).
[16:21:44.079]     INFO: Test took 4170ms.
[16:21:44.153]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:44.153]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437603
[16:21:44.153]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step15_C0 .. HR_xeff_CalDelScan_step15_C15
[16:21:44.154]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:44.194]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:44.859]     INFO: Expecting 41600 events.
[16:21:48.352]     INFO: 41600 events read in total (2966ms).
[16:21:48.355]     INFO: Test took 4161ms.
[16:21:48.427]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:48.427]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437628
[16:21:48.427]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step16_C0 .. HR_xeff_CalDelScan_step16_C15
[16:21:48.428]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:48.466]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:49.131]     INFO: Expecting 41600 events.
[16:21:52.630]     INFO: 41600 events read in total (2972ms).
[16:21:52.634]     INFO: Test took 4168ms.
[16:21:52.708]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:52.708]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437702
[16:21:52.708]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step17_C0 .. HR_xeff_CalDelScan_step17_C15
[16:21:52.708]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:52.748]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:53.413]     INFO: Expecting 41600 events.
[16:21:56.910]     INFO: 41600 events read in total (2970ms).
[16:21:56.914]     INFO: Test took 4166ms.
[16:21:56.988]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:21:56.988]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 437902
[16:21:56.988]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step18_C0 .. HR_xeff_CalDelScan_step18_C15
[16:21:56.988]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:21:57.028]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:21:57.696]     INFO: Expecting 41600 events.
[16:22:01.012]     INFO: 41600 events read in total (2789ms).
[16:22:01.015]     INFO: Test took 3987ms.
[16:22:01.088]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:22:01.088]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 430126
[16:22:01.088]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step19_C0 .. HR_xeff_CalDelScan_step19_C15
[16:22:01.088]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:22:01.346]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  0: caldel = 160 eff = 0.984111
[16:22:01.346]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  1: caldel = 168 eff = 0.978269
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  2: caldel = 162 eff = 0.999543
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  3: caldel = 167 eff = 0.999279
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  4: caldel = 158 eff = 0.999207
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  5: caldel = 140 eff = 0.999111
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  6: caldel = 174 eff = 0.999014
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  7: caldel = 171 eff = 0.999087
[16:22:01.347]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  8: caldel = 190 eff = 0.999111
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  9: caldel = 134 eff = 0.998918
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 10: caldel = 156 eff = 0.999014
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 11: caldel = 139 eff = 0.999327
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 12: caldel = 148 eff = 0.999159
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 13: caldel = 120 eff = 0.998173
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 14: caldel = 142 eff = 0.999712
[16:22:01.348]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 15: caldel = 151 eff = 0.999784
[16:23:41.954]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  xpixelalive
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: xpixelalive
[16:23:41.954]     INFO:    ----------------------------------------------------------------------
[16:23:41.954]     INFO:    PixTestHighRate::xPixelAlive() ntrig = 50, vcal = 200
[16:23:41.954]     INFO:    ----------------------------------------------------------------------
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: clk: 4
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: ctr: 4
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: sda: 19
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: tin: 9
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: level: 15
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: triggerdelay: 0
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: clk: 4
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: ctr: 4
[16:23:41.954]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: sda: 19
[16:23:41.955]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: tin: 9
[16:23:41.955]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: level: 15
[16:23:41.955]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: triggerdelay: 20
[16:23:41.973]     INFO: ROC 0 masking pixel 50/5
[16:23:41.973]     INFO: ROC 0 masking pixel 50/6
[16:23:41.973]     INFO: ROC 0 masking pixel 50/7
[16:23:41.973]     INFO: ROC 0 masking pixel 50/8
[16:23:41.973]     INFO: ROC 0 masking pixel 50/9
[16:23:41.973]     INFO: ROC 0 masking pixel 50/10
[16:23:41.973]     INFO: ROC 0 masking pixel 50/11
[16:23:41.973]     INFO: ROC 0 masking pixel 50/12
[16:23:41.973]     INFO: ROC 0 masking pixel 50/13
[16:23:41.973]     INFO: ROC 0 masking pixel 50/15
[16:23:41.973]     INFO: ROC 0 masking pixel 51/3
[16:23:41.973]     INFO: ROC 0 masking pixel 51/4
[16:23:41.973]     INFO: ROC 0 masking pixel 51/5
[16:23:41.973]     INFO: ROC 0 masking pixel 51/6
[16:23:41.973]     INFO: ROC 0 masking pixel 51/7
[16:23:41.973]     INFO: ROC 0 masking pixel 51/8
[16:23:41.973]     INFO: ROC 0 masking pixel 51/9
[16:23:41.973]     INFO: ROC 0 masking pixel 51/10
[16:23:41.973]     INFO: ROC 0 masking pixel 51/11
[16:23:41.973]     INFO: ROC 0 masking pixel 51/12
[16:23:41.973]     INFO: ROC 0 masking pixel 51/13
[16:23:41.973]     INFO: ROC 0 masking pixel 51/14
[16:23:41.973]     INFO: ROC 0 masking pixel 51/15
[16:23:41.973]     INFO: ROC 0 masking pixel 51/16
[16:23:41.973]     INFO: ROC 0 masking pixel 51/17
[16:23:41.973]     INFO: ROC 0 masking pixel 51/18
[16:23:41.973]     INFO: ROC 0 masking pixel 51/19
[16:23:41.973]     INFO: ROC 0 masking pixel 51/20
[16:23:41.973]     INFO: ROC 0 masking pixel 51/21
[16:23:41.973]     INFO: ROC 0 masking pixel 51/22
[16:23:41.973]     INFO: ROC 0 masking pixel 51/23
[16:23:41.973]     INFO: ROC 0 masking pixel 51/24
[16:23:41.973]     INFO: ROC 0 masking pixel 51/25
[16:23:41.973]     INFO: ROC 0 masking pixel 51/26
[16:23:41.974]     INFO: ROC 0 masking pixel 51/27
[16:23:41.974]     INFO: ROC 0 masking pixel 51/28
[16:23:41.974]     INFO: ROC 0 masking pixel 51/29
[16:23:41.974]     INFO: ROC 0 masking pixel 51/30
[16:23:41.974]     INFO: ROC 0 masking pixel 51/31
[16:23:41.974]     INFO: ROC 0 masking pixel 51/32
[16:23:41.974]     INFO: ROC 0 masking pixel 51/33
[16:23:41.974]     INFO: ROC 0 masking pixel 51/34
[16:23:41.974]     INFO: ROC 0 masking pixel 51/35
[16:23:41.974]     INFO: ROC 0 masking pixel 51/36
[16:23:41.974]     INFO: ROC 0 masking pixel 51/37
[16:23:41.974]     INFO: ROC 0 masking pixel 51/38
[16:23:41.974]     INFO: ROC 0 masking pixel 51/39
[16:23:41.974]     INFO: ROC 0 masking pixel 51/40
[16:23:41.974]     INFO: ROC 0 masking pixel 51/41
[16:23:41.974]     INFO: ROC 0 masking pixel 51/42
[16:23:41.974]     INFO: ROC 0 masking pixel 51/43
[16:23:41.974]     INFO: ROC 0 masking pixel 51/44
[16:23:41.974]     INFO: ROC 0 masking pixel 51/45
[16:23:41.974]     INFO: ROC 0 masking pixel 51/46
[16:23:41.974]     INFO: ROC 0 masking pixel 51/47
[16:23:41.974]     INFO: ROC 0 masking pixel 51/48
[16:23:41.974]     INFO: ROC 0 masking pixel 51/49
[16:23:41.974]     INFO: ROC 0 masking pixel 51/50
[16:23:41.974]     INFO: ROC 0 masking pixel 51/51
[16:23:41.974]     INFO: ROC 0 masking pixel 51/56
[16:23:41.974]     INFO: ROC 0 masking pixel 51/57
[16:23:41.974]     INFO: ROC 0 masking pixel 51/58
[16:23:41.974]     INFO: ROC 0 masking pixel 51/60
[16:23:41.974]     INFO: ROC 0 masking pixel 51/61
[16:23:41.974]     INFO: ROC 0 masking pixel 51/62
[16:23:41.974]     INFO: ROC 1 masking pixel 29/10
[16:23:41.974]     INFO: ROC 1 masking pixel 29/11
[16:23:41.974]     INFO: ROC 1 masking pixel 29/12
[16:23:41.974]     INFO: ROC 1 masking pixel 29/13
[16:23:41.974]     INFO: ROC 1 masking pixel 29/14
[16:23:41.974]     INFO: ROC 1 masking pixel 30/9
[16:23:41.974]     INFO: ROC 1 masking pixel 30/10
[16:23:41.974]     INFO: ROC 1 masking pixel 30/11
[16:23:41.974]     INFO: ROC 1 masking pixel 30/12
[16:23:41.974]     INFO: ROC 1 masking pixel 30/13
[16:23:41.974]     INFO: ROC 1 masking pixel 30/14
[16:23:41.974]     INFO: ROC 1 masking pixel 30/15
[16:23:41.974]     INFO: ROC 1 masking pixel 31/8
[16:23:41.974]     INFO: ROC 1 masking pixel 31/9
[16:23:41.975]     INFO: ROC 1 masking pixel 31/10
[16:23:41.975]     INFO: ROC 1 masking pixel 31/11
[16:23:41.975]     INFO: ROC 1 masking pixel 31/12
[16:23:41.975]     INFO: ROC 1 masking pixel 31/13
[16:23:41.975]     INFO: ROC 1 masking pixel 31/14
[16:23:41.975]     INFO: ROC 1 masking pixel 31/15
[16:23:41.975]     INFO: ROC 1 masking pixel 31/16
[16:23:41.975]     INFO: ROC 1 masking pixel 32/9
[16:23:41.975]     INFO: ROC 1 masking pixel 32/10
[16:23:41.975]     INFO: ROC 1 masking pixel 32/11
[16:23:41.975]     INFO: ROC 1 masking pixel 32/12
[16:23:41.975]     INFO: ROC 1 masking pixel 32/13
[16:23:41.975]     INFO: ROC 1 masking pixel 32/14
[16:23:41.975]     INFO: ROC 1 masking pixel 32/15
[16:23:41.975]     INFO: ROC 1 masking pixel 32/16
[16:23:41.975]     INFO: ROC 1 masking pixel 33/10
[16:23:41.975]     INFO: ROC 1 masking pixel 33/11
[16:23:41.975]     INFO: ROC 1 masking pixel 33/12
[16:23:41.975]     INFO: ROC 1 masking pixel 33/13
[16:23:41.975]     INFO: ROC 1 masking pixel 33/14
[16:23:41.975]     INFO: ROC 1 masking pixel 33/15
[16:23:41.975]     INFO: ROC 1 masking pixel 33/26
[16:23:41.975]     INFO: ROC 1 masking pixel 33/27
[16:23:41.975]     INFO: ROC 1 masking pixel 34/9
[16:23:41.975]     INFO: ROC 1 masking pixel 34/10
[16:23:41.975]     INFO: ROC 1 masking pixel 34/11
[16:23:41.975]     INFO: ROC 1 masking pixel 34/12
[16:23:41.975]     INFO: ROC 1 masking pixel 34/13
[16:23:41.975]     INFO: ROC 1 masking pixel 34/26
[16:23:41.975]     INFO: ROC 1 masking pixel 34/27
[16:23:41.975]     INFO: ROC 1 masking pixel 34/28
[16:23:41.975]     INFO: ROC 1 masking pixel 35/9
[16:23:41.975]     INFO: ROC 1 masking pixel 35/10
[16:23:41.975]     INFO: ROC 1 masking pixel 35/11
[16:23:41.975]     INFO: ROC 1 masking pixel 35/12
[16:23:41.975]     INFO: ROC 1 masking pixel 35/13
[16:23:41.975]     INFO: ROC 1 masking pixel 35/14
[16:23:41.975]     INFO: ROC 1 masking pixel 35/15
[16:23:41.975]     INFO: ROC 1 masking pixel 35/16
[16:23:41.975]     INFO: ROC 1 masking pixel 35/25
[16:23:41.975]     INFO: ROC 1 masking pixel 35/26
[16:23:41.975]     INFO: ROC 1 masking pixel 35/27
[16:23:41.975]     INFO: ROC 1 masking pixel 35/28
[16:23:41.975]     INFO: ROC 1 masking pixel 35/29
[16:23:41.975]     INFO: ROC 1 masking pixel 35/37
[16:23:41.975]     INFO: ROC 1 masking pixel 35/38
[16:23:41.975]     INFO: ROC 1 masking pixel 36/27
[16:23:41.975]     INFO: ROC 1 masking pixel 36/38
[16:23:41.975]     INFO: ROC 1 masking pixel 36/40
[16:23:41.976]     INFO: ROC 1 masking pixel 36/42
[16:23:41.976]     INFO: ROC 1 masking pixel 37/41
[16:23:41.976]     INFO: ROC 1 masking pixel 37/42
[16:23:41.976]     INFO: ROC 1 masking pixel 37/43
[16:23:41.976]     INFO: ROC 1 masking pixel 37/48
[16:23:41.976]     INFO: ROC 1 masking pixel 37/49
[16:23:41.976]     INFO: ROC 1 masking pixel 37/53
[16:23:41.976]     INFO: ROC 1 masking pixel 37/54
[16:23:41.976]     INFO: ROC 1 masking pixel 38/48
[16:23:41.976]     INFO: ROC 1 masking pixel 38/49
[16:23:41.976]     INFO: ROC 1 masking pixel 38/50
[16:23:41.976]     INFO: ROC 1 masking pixel 38/51
[16:23:41.976]     INFO: ROC 1 masking pixel 38/52
[16:23:41.976]     INFO: ROC 1 masking pixel 38/53
[16:23:41.976]     INFO: ROC 1 masking pixel 38/54
[16:23:41.976]     INFO: ROC 1 masking pixel 39/51
[16:23:41.976]     INFO: ROC 1 masking pixel 39/52
[16:23:41.976]     INFO: ROC 1 masking pixel 39/53
[16:23:41.976]     INFO: ROC 1 masking pixel 39/54
[16:23:41.976]     INFO: ROC 1 masking pixel 39/55
[16:23:41.976]     INFO: ROC 1 masking pixel 39/56
[16:23:41.976]     INFO: ROC 1 masking pixel 39/57
[16:23:41.976]     INFO: ROC 1 masking pixel 39/58
[16:23:41.976]     INFO: ROC 1 masking pixel 40/53
[16:23:41.976]     INFO: ROC 1 masking pixel 40/57
[16:23:41.976]     INFO: ROC 1 masking pixel 40/58
[16:23:41.976]     INFO: ROC 1 masking pixel 40/59
[16:23:41.976]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:23:42.647]     INFO: Expecting 208000 events.
[16:23:55.897]     INFO: 208000 events read in total (12723ms).
[16:23:55.909]     INFO: Test took 13933ms.
[16:23:56.337]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:23:56.337]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 1907667
[16:23:56.337]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists highRate_C0 .. highRate_C15
[16:23:56.337]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:23:56.699]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:23:56.699]     INFO: number of red-efficiency pixels:   133  150  148  195  239  208  222  242  195  212  245  225  166  184   71   85
[16:23:56.699]     INFO: number of X-ray hits detected:    62503 13766 92347 137262 145624 143013 150844 141064 155342 152299 149312 141334 141442 89786 58493 66831
[16:23:56.699]     INFO: number of triggers sent (total per ROC):  208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000
[16:23:56.699]     INFO: number of Vcal hits detected:  204680 203429 207845 207804 207753 207787 207773 207750 207800 207777 207751 207767 207827 207807 207926 207915
[16:23:56.699]     INFO: Vcal hit fiducial efficiency (%):  100.0 100.0 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 100.0 100.0
[16:23:56.699]     INFO: Vcal hit overall efficiency (%):  98.4 97.8 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 99.9 100.0 100.0
[16:23:56.699]     INFO: X-ray hit rate [MHz/cm2]:  18.3 4.0 27.1 40.2 42.7 41.9 44.2 41.3 45.5 44.6 43.8 41.4 41.5 26.3 17.1 19.6
[16:23:56.699]     INFO: PixTestHighRate::doXPixelAlive() done
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: clk: 4
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: ctr: 4
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: sda: 19
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: tin: 9
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: level: 15
[16:23:56.748]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: triggerdelay: 0
[16:23:56.748]     INFO: PixTest::       pg_setup set to default.
[16:25:47.186]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:25:47.186]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = highRate_xraymap_C10_V0 -> highRate_xraymap_mod
[16:25:48.882]    DEBUG: <PixGui.cc/handleButtons:L396> PixGui::exit called
[16:25:48.883]    DEBUG: <PixGui.cc/CloseWindow:L335> Final Analog Current: 398.7mA
[16:25:48.884]    DEBUG: <PixGui.cc/CloseWindow:L336> Final Digital Current: 470.3mA
[16:25:48.884]    DEBUG: <PixGui.cc/CloseWindow:L337> Final Module Temperature: -0.4 C
[16:25:48.884]    DEBUG: <PixTestBBMap.cc/~PixTestBBMap:L97> PixTestBBMap dtor
[16:25:48.884]    DEBUG: <PixTestBB2Map.cc/~PixTestBB2Map:L115> PixTestBB2Map dtor
[16:25:48.884]    DEBUG: <PixTestBB3Map.cc/~PixTestBB3Map:L99> PixTestBB3Map dtor
[16:25:48.884]    DEBUG: <PixTestBB4Map.cc/~PixTestBB4Map:L118> PixTestBB4Map dtor
[16:25:48.884]    DEBUG: <PixTestCmd.cc/~PixTestCmd:L78> PixTestCmd dtor
[16:25:48.884]    DEBUG: <PixTestDaq.cc/~PixTestDaq:L37> PixTestDaq dtor
[16:25:48.884]    DEBUG: <PixTestDacDacScan.cc/~PixTestDacDacScan:L136> PixTestDacDacScan dtor
[16:25:48.884]    DEBUG: <PixTestDacScan.cc/~PixTestDacScan:L129> PixTestDacScan dtor
[16:25:48.884]    DEBUG: <PixTestGainPedestal.cc/~PixTestGainPedestal:L125> PixTestGainPedestal dtor
[16:25:48.884]    DEBUG: <PixTestHighRate.cc/~PixTestHighRate:L258> PixTestHighRate dtor
[16:25:48.976]    DEBUG: <PixTestIV.cc/~PixTestIV:L96> PixTestIV dtor
[16:25:48.976]    DEBUG: <PixTestAlive.cc/~PixTestAlive:L115> PixTestAlive dtor
[16:25:48.985]    DEBUG: <PixTestPretest.cc/~PixTestPretest:L136> PixTestPretest dtor
[16:25:48.985]    DEBUG: <PixTestReadback.cc/~PixTestReadback:L89> PixTestReadback dtor, saving tree ... 
[16:25:48.985]    DEBUG: <PixTestScurves.cc/~PixTestScurves:L142> PixTestScurves dtor
[16:25:48.985]    DEBUG: <PixTestTiming.cc/~PixTestTiming:L96> PixTestTiming dtor
[16:25:48.985]    DEBUG: <PixTestTrim.cc/~PixTestTrim:L103> PixTestTrim dtor
[16:25:48.985]    DEBUG: <PixTestXray.cc/~PixTestXray:L218> PixTestXray dtor
[16:25:48.988]    QUIET: Connection to board 58 closed.
[16:25:50.190]    DEBUG: <PixMonitor.cc/dumpSummaries:L39> PixMonitor::dumpSummaries
									 
									
									
															
						
							
						
						[16:16:52.833]     INFO: *** Welcome to pxar ***
[16:16:52.834]     INFO: *** Today: 2016/09/07
[16:16:52.858]     INFO: *** Version: v1.9.0-818-g96727
[16:16:52.858]     INFO: readRocDacs: data/mp315/dacParameters35_C0.dat .. data/mp315/dacParameters35_C15.dat
[16:16:52.859]     INFO: readTbmDacs: data/mp315/tbmParameters_C0a.dat .. data/mp315/tbmParameters_C0b.dat
[16:16:52.860]     INFO: readMaskFile: data/mp315/defaultMaskFile.dat
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 5
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 6
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 7
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 8
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 9
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 10
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 11
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 12
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 13
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 50 15
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 3
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 4
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 5
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 6
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 7
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 8
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 9
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 10
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 11
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 12
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 13
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 14
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 15
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 16
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 17
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 18
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 19
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 20
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 21
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 22
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 23
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 24
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 25
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 26
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 27
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 28
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 29
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 30
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 31
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 32
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 33
[16:16:52.860]     INFO: MASKED Roc 0 col/row: 51 34
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 35
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 36
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 37
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 38
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 39
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 40
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 41
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 42
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 43
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 44
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 45
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 46
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 47
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 48
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 49
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 50
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 51
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 56
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 57
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 58
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 60
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 61
[16:16:52.861]     INFO: MASKED Roc 0 col/row: 51 62
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 29 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 29 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 29 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 29 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 29 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 9
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 30 15
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 8
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 9
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 15
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 31 16
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 9
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 15
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 32 16
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 15
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 26
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 33 27
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 9
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 26
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 27
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 34 28
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 9
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 10
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 11
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 12
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 13
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 14
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 15
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 16
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 25
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 26
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 27
[16:16:52.861]     INFO: MASKED Roc 1 col/row: 35 28
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 35 29
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 35 37
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 35 38
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 36 27
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 36 38
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 36 40
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 36 42
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 41
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 42
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 43
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 48
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 49
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 53
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 37 54
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 48
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 49
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 50
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 51
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 52
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 53
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 38 54
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 51
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 52
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 53
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 54
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 55
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 56
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 57
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 39 58
[16:16:52.862]     INFO: MASKED Roc 1 col/row: 40 53
[16:16:52.863]     INFO: MASKED Roc 1 col/row: 40 57
[16:16:52.863]     INFO: MASKED Roc 1 col/row: 40 58
[16:16:52.863]     INFO: MASKED Roc 1 col/row: 40 59
[16:16:52.863]     INFO: readTrimFile: data/mp315/trimParameters35_C0.dat .. data/mp315/trimParameters35_C15.dat
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 5
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 6
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 7
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 8
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 9
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 10
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 11
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 12
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 13
[16:16:52.866]     INFO:   masking Roc 0 col/row: 50 15
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 3
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 4
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 5
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 6
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 7
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 8
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 9
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 10
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 11
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 12
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 13
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 14
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 15
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 16
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 17
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 18
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 19
[16:16:52.866]     INFO:   masking Roc 0 col/row: 51 20
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 21
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 22
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 23
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 24
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 25
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 26
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 27
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 28
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 29
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 30
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 31
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 32
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 33
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 34
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 35
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 36
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 37
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 38
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 39
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 40
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 41
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 42
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 43
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 44
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 45
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 46
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 47
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 48
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 49
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 50
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 51
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 56
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 57
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 58
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 60
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 61
[16:16:52.867]     INFO:   masking Roc 0 col/row: 51 62
[16:16:52.881]     INFO:   masking Roc 1 col/row: 29 10
[16:16:52.881]     INFO:   masking Roc 1 col/row: 29 11
[16:16:52.881]     INFO:   masking Roc 1 col/row: 29 12
[16:16:52.881]     INFO:   masking Roc 1 col/row: 29 13
[16:16:52.881]     INFO:   masking Roc 1 col/row: 29 14
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 9
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 10
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 11
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 12
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 13
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 14
[16:16:52.881]     INFO:   masking Roc 1 col/row: 30 15
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 8
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 9
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 10
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 11
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 12
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 13
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 14
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 15
[16:16:52.882]     INFO:   masking Roc 1 col/row: 31 16
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 9
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 10
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 11
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 12
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 13
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 14
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 15
[16:16:52.882]     INFO:   masking Roc 1 col/row: 32 16
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 10
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 11
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 12
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 13
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 14
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 15
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 26
[16:16:52.882]     INFO:   masking Roc 1 col/row: 33 27
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 9
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 10
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 11
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 12
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 13
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 26
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 27
[16:16:52.882]     INFO:   masking Roc 1 col/row: 34 28
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 9
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 10
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 11
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 12
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 13
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 14
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 15
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 16
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 25
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 26
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 27
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 28
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 29
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 37
[16:16:52.882]     INFO:   masking Roc 1 col/row: 35 38
[16:16:52.882]     INFO:   masking Roc 1 col/row: 36 27
[16:16:52.882]     INFO:   masking Roc 1 col/row: 36 38
[16:16:52.883]     INFO:   masking Roc 1 col/row: 36 40
[16:16:52.883]     INFO:   masking Roc 1 col/row: 36 42
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 41
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 42
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 43
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 48
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 49
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 53
[16:16:52.883]     INFO:   masking Roc 1 col/row: 37 54
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 48
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 49
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 50
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 51
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 52
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 53
[16:16:52.883]     INFO:   masking Roc 1 col/row: 38 54
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 51
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 52
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 53
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 54
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 55
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 56
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 57
[16:16:52.883]     INFO:   masking Roc 1 col/row: 39 58
[16:16:52.883]     INFO:   masking Roc 1 col/row: 40 53
[16:16:52.883]     INFO:   masking Roc 1 col/row: 40 57
[16:16:52.883]     INFO:   masking Roc 1 col/row: 40 58
[16:16:52.883]     INFO:   masking Roc 1 col/row: 40 59
[16:16:53.025]     INFO:         clk: 4
[16:16:53.025]     INFO:         ctr: 4
[16:16:53.025]     INFO:         sda: 19
[16:16:53.025]     INFO:         tin: 9
[16:16:53.025]     INFO:         level: 15
[16:16:53.025]     INFO:         triggerdelay: 0
[16:16:53.025]    QUIET: Instanciating API for pxar v1.9.0+818~g9672706
[16:16:53.025]     INFO: Log level: DEBUG
[16:16:53.037]    QUIET: Connection to board DTB_WRPRHI opened.
[16:16:53.040]     INFO: DTB startup information
--- DTB info------------------------------------------
Board id:    58
HW version:  DTB1.2
FW version:  4.2
SW version:  4.5
USB id:      DTB_WRPRHI
MAC address: 40D85511803A
Hostname:    pixelDTB058
Comment:     
------------------------------------------------------
[16:16:53.043]     INFO: RPC call hashes of host and DTB match: 398089610
[16:16:54.646]     INFO: DUT info: 
[16:16:54.646]     INFO: The DUT currently contains the following objects:
[16:16:54.646]     INFO:  2 TBM Cores tbm08c (2 ON)
[16:16:54.646]     INFO: 	TBM Core alpha (0): 7 registers set
[16:16:54.646]     INFO: 	TBM Core beta  (1): 7 registers set
[16:16:54.646]     INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[16:16:54.646]     INFO: 	ROC 0: 19 DACs set, Pixels: 65 masked, 0 active.
[16:16:54.646]     INFO: 	ROC 1: 19 DACs set, Pixels: 90 masked, 0 active.
[16:16:54.646]     INFO: 	ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.646]     INFO: 	ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]     INFO: 	ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB<-
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB2<-
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 222
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   plwidth: 35
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB3<-
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:16:54.647]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB4<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   savecaldelscan: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 100
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   cals: 1
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   caldello: 80
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelhi: 200
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelstep: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomplo: 70
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomphi: 130
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompstep: 5
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   noisypixels: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 255
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   cut: 0.5
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Cmd<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DAQ<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   trgnumber: 5
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqtrg: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   daqseconds: 5
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqseconds: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacDacScan<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1: caldel
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1lo: 0
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1hi: 255
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2: vthrcomp
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2lo: 0
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2hi: 255
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacScan<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox(1)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   allpixels: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   unmasked: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: vcal
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 255
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->GainPedestal<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   showfits: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   extended: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   dumphists: checkbox(0)
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   vcalstep: 10
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   measure: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   fit: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   save: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->HighRate<-
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixels: button
[16:16:54.648]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixelthr: 200
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   runsecondshotpixels: 10
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   savetrimbits: checkbox(1)
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   maskuntrimmable: checkbox(1)
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelscan: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   xpixelalive: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   xnoisemaps: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 100
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: 20
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaq: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 20
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 2
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   triggerdelay: 20
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->IV<-
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   port: /dev/FIXME
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestart: 0
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestop: 600
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestep: 5
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   delay: 1
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   compliance(ua): 100
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PhOptimization<-
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   safetymarginlow: 20
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   saturationvcal: 100
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   quantilesaturation: 0.98
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PixelAlive<-
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   alivetest: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   masktest: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   addressdecodingtest: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Pretest<-
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   programroc: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 100
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   settimings: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   findtiming: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   findworkingpixel: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   setvthrcompcaldel: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 250
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   deltavthrcomp: 50
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   fraccaldel: 0.5
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   savedacs: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Readback<-
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   calibratevd: button
[16:16:54.649]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateva: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateia: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   readbackvbg: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   getcalibratedvbg: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalvd: checkbox(1)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalva: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Scurves<-
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   adjustvcal: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpoutputfile: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: Vcal
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 200
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: -1
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig/step: -1
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   scurves: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Timing<-
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   targetclk: 4
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   clocksdascan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   notokenpass: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   phasescan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   levelscan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   tbmphasescan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   rocdelayscan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   timingtest: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   saveparameters: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Trim<-
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   trim: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 8
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 35
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   trimbits: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Xray<-
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   source: Ag
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   phrun: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 100
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   ratescan: button
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmin: 10
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmax: 80
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   stepseconds: 5
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:16:54.650]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:16:54.652]    DEBUG: <PixSetup.cc/init:L81> PixSetup init start; getCurrentRSS() = 33456128
[16:16:54.652]    DEBUG: <PixSetup.cc/init:L87> fPixTestParameters = 0x1f8b0b0
[16:16:54.652]    DEBUG: <PixSetup.cc/init:L88>  fConfigParameters = 0x1d2d370
[16:16:54.653]    DEBUG: <PixSetup.cc/init:L89>        fPxarMemory = 0x7f8dedd94010
[16:16:54.653]    DEBUG: <PixSetup.cc/init:L90>         fPxarMemHi = 0x7f8df3fff510
[16:16:54.653]    DEBUG: <PixSetup.cc/init:L106> PixSetup init done;  getCurrentRSS() = 33464320 fPxarMemory = 0x7f8dedd94010
[16:16:54.654]    DEBUG: <pXar.cc/main:L223> Initial Analog Current: 393.9mA
[16:16:54.655]    DEBUG: <pXar.cc/main:L224> Initial Digital Current: 471.1mA
[16:16:54.655]    DEBUG: <pXar.cc/main:L225> Initial Module Temperature: -0.2 C
[16:16:55.156]    DEBUG: <PixGui.cc/hvOn:L460> HV set On: 0x237a420
[16:16:55.225]    DEBUG: <PixTestFactory.cc/PixTestFactory:L53> PixTestFactory::PixTestFactory()
[16:16:55.225]    DEBUG: <PixTestBBMap.cc/init:L79> PixTestBBMap::init()
[16:16:55.225]    DEBUG: <PixTestBBMap.cc/PixTestBBMap:L27> PixTestBBMap ctor(PixSetup &a, string, TGTab *)
[16:16:55.233]    DEBUG: <PixTestBB2Map.cc/setParameter:L58> setting fTargetIa    = 24 mA/ROC
[16:16:55.233]    DEBUG: <PixTestBB2Map.cc/init:L97> PixTestBB2Map::init()
[16:16:55.233]    DEBUG: <PixTestBB2Map.cc/PixTestBB2Map:L29> PixTestBB2Map ctor(PixSetup &a, string, TGTab *)
[16:16:55.248]    DEBUG: <PixTestBB3Map.cc/init:L81> PixTestBB3Map::init()
[16:16:55.248]    DEBUG: <PixTestBB3Map.cc/PixTestBB3Map:L29> PixTestBB3Map ctor(PixSetup &a, string, TGTab *)
[16:16:55.268]    DEBUG: <PixTestBB4Map.cc/init:L93> PixTestBB4Map::init()
[16:16:55.268]    DEBUG: <PixTestBB4Map.cc/PixTestBB4Map:L26> PixTestMapeff ctor(PixSetup &a, string, TGTab *)
[16:16:55.283]     INFO: PixTestCmd::init()
[16:16:55.298]    DEBUG: <PixTestDaq.cc/init:L44> PixTestDaq::init()
[16:16:55.298]    DEBUG: <PixTestDaq.cc/PixTestDaq:L22> PixTestDaq ctor(PixSetup &a, string, TGTab *)
[16:16:55.298]     INFO: readGainPedestalParameters data/mp315/phCalibrationFitErr35_C0.dat .. data/mp315/phCalibrationFitErr35_C15.dat
[16:16:55.551]    DEBUG: <PixTestDacDacScan.cc/init:L103> PixTestDacDacScan::init()
[16:16:55.551]    DEBUG: <PixTestDacDacScan.cc/PixTestDacDacScan:L22> PixTestDacDacScan ctor(PixSetup &a, string, TGTab *)
[16:16:55.569]    DEBUG: <PixTestGainPedestal.cc/setParameter:L83> PixTestGainPedestal::PixTest() fVcalStep = 10
[16:16:55.577]    DEBUG: <PixTestHighRate.cc/setParameter:L68>   setting fParTriggerFrequency -> 20
[16:16:55.577]    DEBUG: <PixTestHighRate.cc/init:L211> PixTestHighRate::init()
[16:16:55.577]    DEBUG: <PixTestHighRate.cc/PixTestHighRate:L31> PixTestHighRate ctor(PixSetup &a, string, TGTab *)
[16:16:55.608]    DEBUG: <PixTest.cc/setTestParameter:L637>  setting  ntrig to new value 10
[16:16:55.608]    DEBUG: <PixTestPhOptimization.cc/setParameter:L37>   setting fParNtrig  ->10<- from sval = 10
[16:16:55.608]    DEBUG: <PixTestPhOptimization.cc/setParameter:L42>   setting fSafetyMarginLow  ->20<- from sval = 20
[16:16:55.608]    DEBUG: <PixTestPhOptimization.cc/setParameter:L48>   setting fVcalMax  ->100<- from sval = 100
[16:16:55.608]    DEBUG: <PixTestPhOptimization.cc/setParameter:L53>   setting fQuantMax  ->0.98<- from sval = 0.98
[16:16:55.617]    DEBUG: <PixTestAlive.cc/init:L83> PixTestAlive::init()
[16:16:55.617]    DEBUG: <PixTestAlive.cc/PixTestAlive:L21> PixTestAlive ctor(PixSetup &a, string, TGTab *)
[16:16:55.638]    DEBUG: <PixTestReadback.cc/setParameter:L172> fCalwVd set to 1
[16:16:55.638]    DEBUG: <PixTestReadback.cc/init:L95> PixTestReadback::init()
[16:16:55.638]    DEBUG: <PixTestReadback.cc/PixTestReadback:L22> PixTestReadback ctor(PixSetup &a, string, TGTab *)
[16:16:55.638]     INFO: readReadbackCal: data/mp315/readbackCal_C0.dat .. data/mp315/readbackCal_C15.dat
[16:16:55.655]    DEBUG: <PixTestScurves.cc/setParameter:L93> set fOutputFilename = 
[16:16:55.663]    DEBUG: <PixTestTiming.cc/setParameter:L59> PixTestTiming::PixTest() targetclk = 4
[16:16:55.663]    DEBUG: <PixTestTiming.cc/setParameter:L63> PixTestTiming::PixTest() ntrig = 10
[16:16:55.663]    DEBUG: <PixTestTiming.cc/setParameter:L47> fNoTokenPass: 0
[16:16:55.663]    DEBUG: <PixTestTiming.cc/init:L73> PixTestTiming::init()
[16:16:55.677]    DEBUG: <PixTestXray.cc/init:L135> PixTestXray::init()
[16:16:55.677]    DEBUG: <PixTestXray.cc/PixTestXray:L28> PixTestXray ctor(PixSetup &a, string, TGTab *)
[16:17:01.213]     INFO: ######################################################################
[16:17:01.213]     INFO: PixTestAlive::doTest()
[16:17:01.213]     INFO: ######################################################################
[16:17:01.217]     INFO:    ----------------------------------------------------------------------
[16:17:01.217]     INFO:    PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:17:01.217]     INFO:    ----------------------------------------------------------------------
[16:17:01.219]     INFO: ROC 0 masking pixel 50/5
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[16:17:01.220]     INFO: ROC 1 masking pixel 29/10
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[16:17:01.222]     INFO: ROC 1 masking pixel 39/51
[16:17:01.222]     INFO: ROC 1 masking pixel 39/52
[16:17:01.222]     INFO: ROC 1 masking pixel 39/53
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[16:17:01.222]     INFO: ROC 1 masking pixel 39/55
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[16:17:01.222]     INFO: ROC 1 masking pixel 39/58
[16:17:01.222]     INFO: ROC 1 masking pixel 40/53
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[16:17:01.222]     INFO: ROC 1 masking pixel 40/59
[16:17:01.222]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:01.606]     INFO: Expecting 41600 events.
[16:17:05.998]     INFO: 41600 events read in total (3674ms).
[16:17:06.145]     INFO: Test took 4923ms.
[16:17:06.157]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:06.157]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66405
[16:17:06.157]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists PixelAlive_C0 .. PixelAlive_C15
[16:17:06.434]     INFO: PixTestAlive::aliveTest() done
[16:17:06.434]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:17:06.434]    DEBUG: <PixTestAlive.cc/aliveTest:L199> number of red-efficiency pixels:    88   94   36   51   45   56   55   51   60   58   56   56   49   26   11   28
[16:17:06.435]     INFO: ROC 0 masking pixel 50/5
[16:17:06.435]     INFO: ROC 0 masking pixel 50/6
[16:17:06.435]     INFO: ROC 0 masking pixel 50/7
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[16:17:06.435]     INFO: ROC 0 masking pixel 51/3
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[16:17:06.438]     INFO: ROC 1 masking pixel 39/56
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[16:17:06.438]     INFO: ROC 1 masking pixel 39/58
[16:17:06.438]     INFO: ROC 1 masking pixel 40/53
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[16:17:06.438]     INFO: ROC 1 masking pixel 40/59
[16:17:06.465]     INFO:    ----------------------------------------------------------------------
[16:17:06.465]     INFO:    PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:17:06.465]     INFO:    ----------------------------------------------------------------------
[16:17:06.468]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:06.848]     INFO: Expecting 41600 events.
[16:17:09.962]     INFO: 41600 events read in total (2399ms).
[16:17:09.962]     INFO: Test took 3494ms.
[16:17:09.962]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:09.962]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 0
[16:17:09.962]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists MaskTest_C0 .. MaskTest_C15
[16:17:09.963]     INFO: ROC 0 masking pixel 50/5
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[16:17:09.964]     INFO: ROC 1 masking pixel 29/10
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[16:17:09.965]     INFO: ROC 1 masking pixel 35/9
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[16:17:09.966]     INFO: ROC 1 masking pixel 36/27
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[16:17:09.966]     INFO: ROC 1 masking pixel 39/51
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[16:17:09.966]     INFO: ROC 1 masking pixel 40/53
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[16:17:09.966]     INFO: ROC 1 masking pixel 40/59
[16:17:09.966]     INFO: mask vs. old pixelAlive PixelAlive_C0_V0 ..  PixelAlive_C15_V0
[16:17:10.385]     INFO: PixTestAlive::maskTest() done
[16:17:10.386]     INFO: number of mask-defect pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:17:10.386]     INFO: ROC 0 masking pixel 50/5
[16:17:10.386]     INFO: ROC 0 masking pixel 50/6
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[16:17:10.386]     INFO: ROC 0 masking pixel 51/3
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[16:17:10.387]     INFO: ROC 1 masking pixel 29/10
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[16:17:10.389]     INFO: ROC 1 masking pixel 40/59
[16:17:10.408]     INFO:    ----------------------------------------------------------------------
[16:17:10.408]     INFO:    PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:17:10.409]     INFO:    ----------------------------------------------------------------------
[16:17:10.411]     INFO: ROC 0 masking pixel 50/5
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[16:17:10.411]     INFO: ROC 0 masking pixel 51/3
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[16:17:10.412]     INFO: ROC 1 masking pixel 29/10
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[16:17:10.414]     INFO: ROC 1 masking pixel 39/51
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[16:17:10.414]     INFO: ROC 1 masking pixel 40/59
[16:17:10.414]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:10.791]     INFO: Expecting 41600 events.
[16:17:15.181]     INFO: 41600 events read in total (3675ms).
[16:17:15.183]     INFO: Test took 4769ms.
[16:17:15.192]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:15.192]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66405
[16:17:15.192]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists AddressDecodingTest_C0 .. AddressDecodingTest_C15
[16:17:15.562]     INFO: PixTestAlive::addressDecodingTest() done
[16:17:15.562]     INFO: number of address-decoding pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:17:15.562]     INFO: ROC 0 masking pixel 50/5
[16:17:15.562]     INFO: ROC 0 masking pixel 50/6
[16:17:15.562]     INFO: ROC 0 masking pixel 50/7
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[16:17:15.563]     INFO: ROC 0 masking pixel 51/3
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[16:17:15.564]     INFO: ROC 1 masking pixel 29/10
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[16:17:15.565]     INFO: ROC 1 masking pixel 38/53
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[16:17:15.565]     INFO: ROC 1 masking pixel 39/51
[16:17:15.565]     INFO: ROC 1 masking pixel 39/52
[16:17:15.565]     INFO: ROC 1 masking pixel 39/53
[16:17:15.565]     INFO: ROC 1 masking pixel 39/54
[16:17:15.565]     INFO: ROC 1 masking pixel 39/55
[16:17:15.565]     INFO: ROC 1 masking pixel 39/56
[16:17:15.566]     INFO: ROC 1 masking pixel 39/57
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[16:17:15.566]     INFO: ROC 1 masking pixel 40/53
[16:17:15.566]     INFO: ROC 1 masking pixel 40/57
[16:17:15.566]     INFO: ROC 1 masking pixel 40/58
[16:17:15.566]     INFO: ROC 1 masking pixel 40/59
[16:17:15.566]     INFO: PixTestAlive::doTest() done, duration: 14 seconds
[16:17:26.090]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  caldelscan
[16:17:26.090]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: caldelscan
[16:17:26.090]     INFO:    ----------------------------------------------------------------------
[16:17:26.090]     INFO:    PixTestHighRate::calDelScan() ntrig = 10, vcal = 200
[16:17:26.090]     INFO:    ----------------------------------------------------------------------
[16:17:26.229]     INFO: Expecting 768 events.
[16:17:27.363]     INFO: 768 events read in total (418ms).
[16:17:27.363]     INFO: Test took 1267ms.
[16:17:27.366]     INFO: ROC 0 masking pixel 50/5
[16:17:27.366]     INFO: ROC 0 masking pixel 50/6
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[16:17:27.367]     INFO: ROC 0 masking pixel 51/3
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[16:17:27.368]     INFO: ROC 1 masking pixel 29/10
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[16:17:27.369]     INFO: ROC 1 masking pixel 33/10
[16:17:27.369]     INFO: ROC 1 masking pixel 33/11
[16:17:27.369]     INFO: ROC 1 masking pixel 33/12
[16:17:27.369]     INFO: ROC 1 masking pixel 33/13
[16:17:27.369]     INFO: ROC 1 masking pixel 33/14
[16:17:27.369]     INFO: ROC 1 masking pixel 33/15
[16:17:27.369]     INFO: ROC 1 masking pixel 33/26
[16:17:27.369]     INFO: ROC 1 masking pixel 33/27
[16:17:27.369]     INFO: ROC 1 masking pixel 34/9
[16:17:27.369]     INFO: ROC 1 masking pixel 34/10
[16:17:27.369]     INFO: ROC 1 masking pixel 34/11
[16:17:27.369]     INFO: ROC 1 masking pixel 34/12
[16:17:27.369]     INFO: ROC 1 masking pixel 34/13
[16:17:27.369]     INFO: ROC 1 masking pixel 34/26
[16:17:27.369]     INFO: ROC 1 masking pixel 34/27
[16:17:27.369]     INFO: ROC 1 masking pixel 34/28
[16:17:27.369]     INFO: ROC 1 masking pixel 35/9
[16:17:27.369]     INFO: ROC 1 masking pixel 35/10
[16:17:27.369]     INFO: ROC 1 masking pixel 35/11
[16:17:27.369]     INFO: ROC 1 masking pixel 35/12
[16:17:27.369]     INFO: ROC 1 masking pixel 35/13
[16:17:27.369]     INFO: ROC 1 masking pixel 35/14
[16:17:27.369]     INFO: ROC 1 masking pixel 35/15
[16:17:27.369]     INFO: ROC 1 masking pixel 35/16
[16:17:27.369]     INFO: ROC 1 masking pixel 35/25
[16:17:27.369]     INFO: ROC 1 masking pixel 35/26
[16:17:27.369]     INFO: ROC 1 masking pixel 35/27
[16:17:27.369]     INFO: ROC 1 masking pixel 35/28
[16:17:27.369]     INFO: ROC 1 masking pixel 35/29
[16:17:27.369]     INFO: ROC 1 masking pixel 35/37
[16:17:27.369]     INFO: ROC 1 masking pixel 35/38
[16:17:27.369]     INFO: ROC 1 masking pixel 36/27
[16:17:27.369]     INFO: ROC 1 masking pixel 36/38
[16:17:27.369]     INFO: ROC 1 masking pixel 36/40
[16:17:27.369]     INFO: ROC 1 masking pixel 36/42
[16:17:27.369]     INFO: ROC 1 masking pixel 37/41
[16:17:27.369]     INFO: ROC 1 masking pixel 37/42
[16:17:27.369]     INFO: ROC 1 masking pixel 37/43
[16:17:27.369]     INFO: ROC 1 masking pixel 37/48
[16:17:27.369]     INFO: ROC 1 masking pixel 37/49
[16:17:27.369]     INFO: ROC 1 masking pixel 37/53
[16:17:27.369]     INFO: ROC 1 masking pixel 37/54
[16:17:27.369]     INFO: ROC 1 masking pixel 38/48
[16:17:27.369]     INFO: ROC 1 masking pixel 38/49
[16:17:27.369]     INFO: ROC 1 masking pixel 38/50
[16:17:27.369]     INFO: ROC 1 masking pixel 38/51
[16:17:27.369]     INFO: ROC 1 masking pixel 38/52
[16:17:27.369]     INFO: ROC 1 masking pixel 38/53
[16:17:27.369]     INFO: ROC 1 masking pixel 38/54
[16:17:27.369]     INFO: ROC 1 masking pixel 39/51
[16:17:27.370]     INFO: ROC 1 masking pixel 39/52
[16:17:27.370]     INFO: ROC 1 masking pixel 39/53
[16:17:27.370]     INFO: ROC 1 masking pixel 39/54
[16:17:27.370]     INFO: ROC 1 masking pixel 39/55
[16:17:27.370]     INFO: ROC 1 masking pixel 39/56
[16:17:27.370]     INFO: ROC 1 masking pixel 39/57
[16:17:27.370]     INFO: ROC 1 masking pixel 39/58
[16:17:27.370]     INFO: ROC 1 masking pixel 40/53
[16:17:27.370]     INFO: ROC 1 masking pixel 40/57
[16:17:27.370]     INFO: ROC 1 masking pixel 40/58
[16:17:27.370]     INFO: ROC 1 masking pixel 40/59
[16:17:27.372]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:28.167]     INFO: Expecting 41600 events.
[16:17:31.770]     INFO: 41600 events read in total (3077ms).
[16:17:31.775]     INFO: Test took 4403ms.
[16:17:31.889]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:31.889]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 636641
[16:17:31.889]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step0_C0 .. HR_xeff_CalDelScan_step0_C15
[16:17:31.889]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:31.938]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:32.603]     INFO: Expecting 41600 events.
[16:17:36.281]     INFO: 41600 events read in total (3151ms).
[16:17:36.285]     INFO: Test took 4347ms.
[16:17:36.394]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:36.394]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 640692
[16:17:36.394]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step1_C0 .. HR_xeff_CalDelScan_step1_C15
[16:17:36.395]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:36.445]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:37.110]     INFO: Expecting 41600 events.
[16:17:40.827]     INFO: 41600 events read in total (3190ms).
[16:17:40.831]     INFO: Test took 4386ms.
[16:17:40.944]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:40.944]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643087
[16:17:40.944]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step2_C0 .. HR_xeff_CalDelScan_step2_C15
[16:17:40.944]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:40.999]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:41.664]     INFO: Expecting 41600 events.
[16:17:45.381]     INFO: 41600 events read in total (3190ms).
[16:17:45.386]     INFO: Test took 4387ms.
[16:17:45.495]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:45.495]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642063
[16:17:45.495]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step3_C0 .. HR_xeff_CalDelScan_step3_C15
[16:17:45.496]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:45.547]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:46.212]     INFO: Expecting 41600 events.
[16:17:49.957]     INFO: 41600 events read in total (3219ms).
[16:17:49.961]     INFO: Test took 4414ms.
[16:17:50.069]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:50.069]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643830
[16:17:50.069]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step4_C0 .. HR_xeff_CalDelScan_step4_C15
[16:17:50.069]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:50.120]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:50.785]     INFO: Expecting 41600 events.
[16:17:54.506]     INFO: 41600 events read in total (3194ms).
[16:17:54.510]     INFO: Test took 4390ms.
[16:17:54.620]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:54.620]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643975
[16:17:54.620]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step5_C0 .. HR_xeff_CalDelScan_step5_C15
[16:17:54.620]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:54.671]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:55.336]     INFO: Expecting 41600 events.
[16:17:59.053]     INFO: 41600 events read in total (3190ms).
[16:17:59.057]     INFO: Test took 4386ms.
[16:17:59.168]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:59.168]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642839
[16:17:59.168]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step6_C0 .. HR_xeff_CalDelScan_step6_C15
[16:17:59.169]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:17:59.221]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:17:59.892]     INFO: Expecting 41600 events.
[16:18:03.650]     INFO: 41600 events read in total (3231ms).
[16:18:03.654]     INFO: Test took 4433ms.
[16:18:03.765]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:03.765]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 644121
[16:18:03.766]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step7_C0 .. HR_xeff_CalDelScan_step7_C15
[16:18:03.766]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:03.817]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:04.482]     INFO: Expecting 41600 events.
[16:18:08.201]     INFO: 41600 events read in total (3192ms).
[16:18:08.205]     INFO: Test took 4388ms.
[16:18:08.314]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:08.315]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643044
[16:18:08.315]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step8_C0 .. HR_xeff_CalDelScan_step8_C15
[16:18:08.315]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:08.365]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:09.031]     INFO: Expecting 41600 events.
[16:18:12.780]     INFO: 41600 events read in total (3222ms).
[16:18:12.784]     INFO: Test took 4419ms.
[16:18:12.892]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:12.892]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643910
[16:18:12.892]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step9_C0 .. HR_xeff_CalDelScan_step9_C15
[16:18:12.893]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:12.944]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:13.609]     INFO: Expecting 41600 events.
[16:18:17.342]     INFO: 41600 events read in total (3206ms).
[16:18:17.347]     INFO: Test took 4403ms.
[16:18:17.456]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:17.456]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642081
[16:18:17.456]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step10_C0 .. HR_xeff_CalDelScan_step10_C15
[16:18:17.456]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:17.507]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:18.172]     INFO: Expecting 41600 events.
[16:18:21.946]     INFO: 41600 events read in total (3247ms).
[16:18:21.951]     INFO: Test took 4444ms.
[16:18:22.061]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:22.061]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 644413
[16:18:22.061]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step11_C0 .. HR_xeff_CalDelScan_step11_C15
[16:18:22.062]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:22.115]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:22.782]     INFO: Expecting 41600 events.
[16:18:26.518]     INFO: 41600 events read in total (3210ms).
[16:18:26.523]     INFO: Test took 4408ms.
[16:18:26.632]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:26.632]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642748
[16:18:26.632]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step12_C0 .. HR_xeff_CalDelScan_step12_C15
[16:18:26.632]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:26.683]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:27.349]     INFO: Expecting 41600 events.
[16:18:31.083]     INFO: 41600 events read in total (3208ms).
[16:18:31.088]     INFO: Test took 4405ms.
[16:18:31.199]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:31.199]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642684
[16:18:31.199]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step13_C0 .. HR_xeff_CalDelScan_step13_C15
[16:18:31.199]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:31.251]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:31.918]     INFO: Expecting 41600 events.
[16:18:35.673]     INFO: 41600 events read in total (3228ms).
[16:18:35.677]     INFO: Test took 4426ms.
[16:18:35.785]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:35.785]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 642523
[16:18:35.785]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step14_C0 .. HR_xeff_CalDelScan_step14_C15
[16:18:35.786]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:35.837]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:36.503]     INFO: Expecting 41600 events.
[16:18:40.225]     INFO: 41600 events read in total (3196ms).
[16:18:40.231]     INFO: Test took 4394ms.
[16:18:40.341]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:40.341]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 644546
[16:18:40.341]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step15_C0 .. HR_xeff_CalDelScan_step15_C15
[16:18:40.342]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:40.393]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:41.058]     INFO: Expecting 41600 events.
[16:18:44.797]     INFO: 41600 events read in total (3212ms).
[16:18:44.802]     INFO: Test took 4409ms.
[16:18:44.910]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:44.910]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643316
[16:18:44.910]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step16_C0 .. HR_xeff_CalDelScan_step16_C15
[16:18:44.911]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:44.962]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:45.627]     INFO: Expecting 41600 events.
[16:18:49.379]     INFO: 41600 events read in total (3225ms).
[16:18:49.383]     INFO: Test took 4421ms.
[16:18:49.492]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:49.492]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 643418
[16:18:49.492]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step17_C0 .. HR_xeff_CalDelScan_step17_C15
[16:18:49.493]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:49.544]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:50.209]     INFO: Expecting 41600 events.
[16:18:53.899]     INFO: 41600 events read in total (3163ms).
[16:18:53.904]     INFO: Test took 4360ms.
[16:18:54.014]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:54.014]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 641538
[16:18:54.014]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step18_C0 .. HR_xeff_CalDelScan_step18_C15
[16:18:54.015]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:54.067]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:18:54.734]     INFO: Expecting 41600 events.
[16:18:58.288]     INFO: 41600 events read in total (3027ms).
[16:18:58.293]     INFO: Test took 4226ms.
[16:18:58.398]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:18:58.398]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 635923
[16:18:58.398]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step19_C0 .. HR_xeff_CalDelScan_step19_C15
[16:18:58.399]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:18:58.670]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  0: caldel = 142 eff = 0.984038
[16:18:58.670]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  1: caldel = 146 eff = 0.978317
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  2: caldel = 172 eff = 0.999038
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  3: caldel = 164 eff = 0.997981
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  4: caldel = 161 eff = 0.998077
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  5: caldel = 146 eff = 0.997764
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  6: caldel = 171 eff = 0.997981
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  7: caldel = 177 eff = 0.998053
[16:18:58.671]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  8: caldel = 192 eff = 0.997716
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  9: caldel = 138 eff = 0.997837
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 10: caldel = 167 eff = 0.997837
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 11: caldel = 141 eff = 0.997981
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 12: caldel = 151 eff = 0.998053
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 13: caldel = 125 eff = 0.995625
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 14: caldel = 126 eff = 0.999543
[16:18:58.672]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 15: caldel = 149 eff = 0.999471
[16:19:29.146]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  xpixelalive
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: xpixelalive
[16:19:29.146]     INFO:    ----------------------------------------------------------------------
[16:19:29.146]     INFO:    PixTestHighRate::xPixelAlive() ntrig = 50, vcal = 200
[16:19:29.146]     INFO:    ----------------------------------------------------------------------
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: clk: 4
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: ctr: 4
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: sda: 19
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: tin: 9
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: level: 15
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: triggerdelay: 0
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: clk: 4
[16:19:29.146]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: ctr: 4
[16:19:29.147]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: sda: 19
[16:19:29.147]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: tin: 9
[16:19:29.147]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: level: 15
[16:19:29.147]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: triggerdelay: 20
[16:19:29.165]     INFO: ROC 0 masking pixel 50/5
[16:19:29.165]     INFO: ROC 0 masking pixel 50/6
[16:19:29.165]     INFO: ROC 0 masking pixel 50/7
[16:19:29.165]     INFO: ROC 0 masking pixel 50/8
[16:19:29.165]     INFO: ROC 0 masking pixel 50/9
[16:19:29.165]     INFO: ROC 0 masking pixel 50/10
[16:19:29.165]     INFO: ROC 0 masking pixel 50/11
[16:19:29.165]     INFO: ROC 0 masking pixel 50/12
[16:19:29.165]     INFO: ROC 0 masking pixel 50/13
[16:19:29.165]     INFO: ROC 0 masking pixel 50/15
[16:19:29.165]     INFO: ROC 0 masking pixel 51/3
[16:19:29.165]     INFO: ROC 0 masking pixel 51/4
[16:19:29.165]     INFO: ROC 0 masking pixel 51/5
[16:19:29.165]     INFO: ROC 0 masking pixel 51/6
[16:19:29.165]     INFO: ROC 0 masking pixel 51/7
[16:19:29.165]     INFO: ROC 0 masking pixel 51/8
[16:19:29.165]     INFO: ROC 0 masking pixel 51/9
[16:19:29.165]     INFO: ROC 0 masking pixel 51/10
[16:19:29.165]     INFO: ROC 0 masking pixel 51/11
[16:19:29.165]     INFO: ROC 0 masking pixel 51/12
[16:19:29.165]     INFO: ROC 0 masking pixel 51/13
[16:19:29.165]     INFO: ROC 0 masking pixel 51/14
[16:19:29.165]     INFO: ROC 0 masking pixel 51/15
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[16:19:29.166]     INFO: ROC 0 masking pixel 51/39
[16:19:29.166]     INFO: ROC 0 masking pixel 51/40
[16:19:29.166]     INFO: ROC 0 masking pixel 51/41
[16:19:29.166]     INFO: ROC 0 masking pixel 51/42
[16:19:29.166]     INFO: ROC 0 masking pixel 51/43
[16:19:29.166]     INFO: ROC 0 masking pixel 51/44
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[16:19:29.166]     INFO: ROC 0 masking pixel 51/46
[16:19:29.166]     INFO: ROC 0 masking pixel 51/47
[16:19:29.166]     INFO: ROC 0 masking pixel 51/48
[16:19:29.166]     INFO: ROC 0 masking pixel 51/49
[16:19:29.166]     INFO: ROC 0 masking pixel 51/50
[16:19:29.166]     INFO: ROC 0 masking pixel 51/51
[16:19:29.166]     INFO: ROC 0 masking pixel 51/56
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[16:19:29.166]     INFO: ROC 0 masking pixel 51/58
[16:19:29.166]     INFO: ROC 0 masking pixel 51/60
[16:19:29.166]     INFO: ROC 0 masking pixel 51/61
[16:19:29.166]     INFO: ROC 0 masking pixel 51/62
[16:19:29.166]     INFO: ROC 1 masking pixel 29/10
[16:19:29.166]     INFO: ROC 1 masking pixel 29/11
[16:19:29.166]     INFO: ROC 1 masking pixel 29/12
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[16:19:29.166]     INFO: ROC 1 masking pixel 29/14
[16:19:29.166]     INFO: ROC 1 masking pixel 30/9
[16:19:29.166]     INFO: ROC 1 masking pixel 30/10
[16:19:29.166]     INFO: ROC 1 masking pixel 30/11
[16:19:29.166]     INFO: ROC 1 masking pixel 30/12
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[16:19:29.166]     INFO: ROC 1 masking pixel 30/15
[16:19:29.166]     INFO: ROC 1 masking pixel 31/8
[16:19:29.167]     INFO: ROC 1 masking pixel 31/9
[16:19:29.167]     INFO: ROC 1 masking pixel 31/10
[16:19:29.167]     INFO: ROC 1 masking pixel 31/11
[16:19:29.167]     INFO: ROC 1 masking pixel 31/12
[16:19:29.167]     INFO: ROC 1 masking pixel 31/13
[16:19:29.167]     INFO: ROC 1 masking pixel 31/14
[16:19:29.167]     INFO: ROC 1 masking pixel 31/15
[16:19:29.167]     INFO: ROC 1 masking pixel 31/16
[16:19:29.167]     INFO: ROC 1 masking pixel 32/9
[16:19:29.167]     INFO: ROC 1 masking pixel 32/10
[16:19:29.167]     INFO: ROC 1 masking pixel 32/11
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[16:19:29.167]     INFO: ROC 1 masking pixel 32/13
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[16:19:29.167]     INFO: ROC 1 masking pixel 32/15
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[16:19:29.167]     INFO: ROC 1 masking pixel 33/10
[16:19:29.167]     INFO: ROC 1 masking pixel 33/11
[16:19:29.167]     INFO: ROC 1 masking pixel 33/12
[16:19:29.167]     INFO: ROC 1 masking pixel 33/13
[16:19:29.167]     INFO: ROC 1 masking pixel 33/14
[16:19:29.167]     INFO: ROC 1 masking pixel 33/15
[16:19:29.167]     INFO: ROC 1 masking pixel 33/26
[16:19:29.167]     INFO: ROC 1 masking pixel 33/27
[16:19:29.167]     INFO: ROC 1 masking pixel 34/9
[16:19:29.167]     INFO: ROC 1 masking pixel 34/10
[16:19:29.167]     INFO: ROC 1 masking pixel 34/11
[16:19:29.167]     INFO: ROC 1 masking pixel 34/12
[16:19:29.167]     INFO: ROC 1 masking pixel 34/13
[16:19:29.167]     INFO: ROC 1 masking pixel 34/26
[16:19:29.167]     INFO: ROC 1 masking pixel 34/27
[16:19:29.167]     INFO: ROC 1 masking pixel 34/28
[16:19:29.167]     INFO: ROC 1 masking pixel 35/9
[16:19:29.167]     INFO: ROC 1 masking pixel 35/10
[16:19:29.167]     INFO: ROC 1 masking pixel 35/11
[16:19:29.167]     INFO: ROC 1 masking pixel 35/12
[16:19:29.167]     INFO: ROC 1 masking pixel 35/13
[16:19:29.167]     INFO: ROC 1 masking pixel 35/14
[16:19:29.167]     INFO: ROC 1 masking pixel 35/15
[16:19:29.167]     INFO: ROC 1 masking pixel 35/16
[16:19:29.167]     INFO: ROC 1 masking pixel 35/25
[16:19:29.167]     INFO: ROC 1 masking pixel 35/26
[16:19:29.167]     INFO: ROC 1 masking pixel 35/27
[16:19:29.167]     INFO: ROC 1 masking pixel 35/28
[16:19:29.167]     INFO: ROC 1 masking pixel 35/29
[16:19:29.167]     INFO: ROC 1 masking pixel 35/37
[16:19:29.167]     INFO: ROC 1 masking pixel 35/38
[16:19:29.167]     INFO: ROC 1 masking pixel 36/27
[16:19:29.167]     INFO: ROC 1 masking pixel 36/38
[16:19:29.168]     INFO: ROC 1 masking pixel 36/40
[16:19:29.168]     INFO: ROC 1 masking pixel 36/42
[16:19:29.168]     INFO: ROC 1 masking pixel 37/41
[16:19:29.168]     INFO: ROC 1 masking pixel 37/42
[16:19:29.168]     INFO: ROC 1 masking pixel 37/43
[16:19:29.168]     INFO: ROC 1 masking pixel 37/48
[16:19:29.168]     INFO: ROC 1 masking pixel 37/49
[16:19:29.168]     INFO: ROC 1 masking pixel 37/53
[16:19:29.168]     INFO: ROC 1 masking pixel 37/54
[16:19:29.168]     INFO: ROC 1 masking pixel 38/48
[16:19:29.168]     INFO: ROC 1 masking pixel 38/49
[16:19:29.168]     INFO: ROC 1 masking pixel 38/50
[16:19:29.168]     INFO: ROC 1 masking pixel 38/51
[16:19:29.168]     INFO: ROC 1 masking pixel 38/52
[16:19:29.168]     INFO: ROC 1 masking pixel 38/53
[16:19:29.168]     INFO: ROC 1 masking pixel 38/54
[16:19:29.168]     INFO: ROC 1 masking pixel 39/51
[16:19:29.168]     INFO: ROC 1 masking pixel 39/52
[16:19:29.168]     INFO: ROC 1 masking pixel 39/53
[16:19:29.168]     INFO: ROC 1 masking pixel 39/54
[16:19:29.168]     INFO: ROC 1 masking pixel 39/55
[16:19:29.168]     INFO: ROC 1 masking pixel 39/56
[16:19:29.168]     INFO: ROC 1 masking pixel 39/57
[16:19:29.168]     INFO: ROC 1 masking pixel 39/58
[16:19:29.168]     INFO: ROC 1 masking pixel 40/53
[16:19:29.168]     INFO: ROC 1 masking pixel 40/57
[16:19:29.168]     INFO: ROC 1 masking pixel 40/58
[16:19:29.168]     INFO: ROC 1 masking pixel 40/59
[16:19:29.169]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:19:29.835]     INFO: Expecting 208000 events.
[16:19:44.856]     INFO: 208000 events read in total (14494ms).
[16:19:44.872]     INFO: Test took 15703ms.
[16:19:45.547]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:19:45.547]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 2917816
[16:19:45.547]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists highRate_C0 .. highRate_C15
[16:19:45.547]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:19:45.977]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:19:45.977]     INFO: number of red-efficiency pixels:   211  123  242  361  409  412  461  402  461  475  412  428  415  448  117  127
[16:19:45.977]     INFO: number of X-ray hits detected:    97127 15418 143361 211856 225639 223592 233394 219028 241322 237008 230951 218815 219567 140119 90697 103517
[16:19:45.977]     INFO: number of triggers sent (total per ROC):  208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000
[16:19:45.977]     INFO: number of Vcal hits detected:  204601 203466 207751 207615 207559 207555 207506 207575 207502 207487 207554 207532 207552 207520 207879 207870
[16:19:45.977]     INFO: Vcal hit fiducial efficiency (%):  99.9 100.0 99.9 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.9 99.9
[16:19:45.977]     INFO: Vcal hit overall efficiency (%):  98.4 97.8 99.9 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.8 99.9 99.9
[16:19:45.977]     INFO: X-ray hit rate [MHz/cm2]:  28.5 4.5 42.0 62.1 66.1 65.5 68.4 64.2 70.7 69.5 67.7 64.1 64.4 41.1 26.6 30.3
[16:19:45.977]     INFO: PixTestHighRate::doXPixelAlive() done
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: clk: 4
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: ctr: 4
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: sda: 19
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: tin: 9
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: level: 15
[16:19:46.028]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: triggerdelay: 0
[16:19:46.028]     INFO: PixTest::       pg_setup set to default.
[16:19:49.242]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:19:49.242]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = highRate_xraymap_C12_V0 -> highRate_xraymap_mod
[16:19:50.778]    DEBUG: <PixGui.cc/handleButtons:L396> PixGui::exit called
[16:19:50.779]    DEBUG: <PixGui.cc/CloseWindow:L335> Final Analog Current: 398.7mA
[16:19:50.779]    DEBUG: <PixGui.cc/CloseWindow:L336> Final Digital Current: 471.1mA
[16:19:50.779]    DEBUG: <PixGui.cc/CloseWindow:L337> Final Module Temperature: -0.2 C
[16:19:50.779]    DEBUG: <PixTestBBMap.cc/~PixTestBBMap:L97> PixTestBBMap dtor
[16:19:50.779]    DEBUG: <PixTestBB2Map.cc/~PixTestBB2Map:L115> PixTestBB2Map dtor
[16:19:50.779]    DEBUG: <PixTestBB3Map.cc/~PixTestBB3Map:L99> PixTestBB3Map dtor
[16:19:50.780]    DEBUG: <PixTestBB4Map.cc/~PixTestBB4Map:L118> PixTestBB4Map dtor
[16:19:50.780]    DEBUG: <PixTestCmd.cc/~PixTestCmd:L78> PixTestCmd dtor
[16:19:50.780]    DEBUG: <PixTestDaq.cc/~PixTestDaq:L37> PixTestDaq dtor
[16:19:50.780]    DEBUG: <PixTestDacDacScan.cc/~PixTestDacDacScan:L136> PixTestDacDacScan dtor
[16:19:50.780]    DEBUG: <PixTestDacScan.cc/~PixTestDacScan:L129> PixTestDacScan dtor
[16:19:50.780]    DEBUG: <PixTestGainPedestal.cc/~PixTestGainPedestal:L125> PixTestGainPedestal dtor
[16:19:50.780]    DEBUG: <PixTestHighRate.cc/~PixTestHighRate:L258> PixTestHighRate dtor
[16:19:50.870]    DEBUG: <PixTestIV.cc/~PixTestIV:L96> PixTestIV dtor
[16:19:50.871]    DEBUG: <PixTestAlive.cc/~PixTestAlive:L115> PixTestAlive dtor
[16:19:50.880]    DEBUG: <PixTestPretest.cc/~PixTestPretest:L136> PixTestPretest dtor
[16:19:50.880]    DEBUG: <PixTestReadback.cc/~PixTestReadback:L89> PixTestReadback dtor, saving tree ... 
[16:19:50.880]    DEBUG: <PixTestScurves.cc/~PixTestScurves:L142> PixTestScurves dtor
[16:19:50.880]    DEBUG: <PixTestTiming.cc/~PixTestTiming:L96> PixTestTiming dtor
[16:19:50.880]    DEBUG: <PixTestTrim.cc/~PixTestTrim:L103> PixTestTrim dtor
[16:19:50.880]    DEBUG: <PixTestXray.cc/~PixTestXray:L218> PixTestXray dtor
[16:19:50.882]    QUIET: Connection to board 58 closed.
[16:19:50.961]    DEBUG: <PixMonitor.cc/dumpSummaries:L39> PixMonitor::dumpSummaries
									 
									
									
															
						
							
						
						[16:12:58.088]     INFO: *** Welcome to pxar ***
[16:12:58.088]     INFO: *** Today: 2016/09/07
[16:12:58.112]     INFO: *** Version: v1.9.0-818-g96727
[16:12:58.112]     INFO: readRocDacs: data/mp315/dacParameters35_C0.dat .. data/mp315/dacParameters35_C15.dat
[16:12:58.113]     INFO: readTbmDacs: data/mp315/tbmParameters_C0a.dat .. data/mp315/tbmParameters_C0b.dat
[16:12:58.113]     INFO: readMaskFile: data/mp315/defaultMaskFile.dat
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 5
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 6
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 7
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 8
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 9
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 10
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 11
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 12
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 13
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 50 15
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 3
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 4
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 5
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 6
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 7
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 8
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 9
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 10
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 11
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 12
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 13
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 14
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 15
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 16
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 17
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 18
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 19
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 20
[16:12:58.113]     INFO: MASKED Roc 0 col/row: 51 21
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 22
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 23
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 24
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 25
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 26
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 27
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 28
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 29
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 30
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 31
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 32
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 33
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 34
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 35
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 36
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 37
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 38
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 39
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 40
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 41
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 42
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 43
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 44
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 45
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 46
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 47
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 48
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 49
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 50
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 51
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 56
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 57
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 58
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 60
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 61
[16:12:58.114]     INFO: MASKED Roc 0 col/row: 51 62
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 29 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 29 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 29 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 29 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 29 14
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 9
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 14
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 30 15
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 8
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 9
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 14
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 15
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 31 16
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 9
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 14
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 15
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 32 16
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 14
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 15
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 26
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 33 27
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 9
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 10
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 11
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 12
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 13
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 26
[16:12:58.114]     INFO: MASKED Roc 1 col/row: 34 27
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 34 28
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 9
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 10
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 11
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 12
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 13
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 14
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 15
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 16
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 25
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 26
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 27
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 28
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 29
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 37
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 35 38
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 36 27
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 36 38
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 36 40
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 36 42
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 41
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 42
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 43
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 48
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 49
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 53
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 37 54
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 48
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 49
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 50
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 51
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 52
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 53
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 38 54
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 51
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 52
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 53
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 54
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 55
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 56
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 57
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 39 58
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 40 53
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 40 57
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 40 58
[16:12:58.115]     INFO: MASKED Roc 1 col/row: 40 59
[16:12:58.115]     INFO: readTrimFile: data/mp315/trimParameters35_C0.dat .. data/mp315/trimParameters35_C15.dat
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 5
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 6
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 7
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 8
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 9
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 10
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 11
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 12
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 13
[16:12:58.116]     INFO:   masking Roc 0 col/row: 50 15
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 3
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 4
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 5
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 6
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 7
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 8
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 9
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 10
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 11
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 12
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 13
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 14
[16:12:58.116]     INFO:   masking Roc 0 col/row: 51 15
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 16
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 17
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 18
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 19
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 20
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 21
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 22
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 23
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 24
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 25
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 26
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 27
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 28
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 29
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 30
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 31
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 32
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 33
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 34
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 35
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 36
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 37
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 38
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 39
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 40
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 41
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 42
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 43
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 44
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 45
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 46
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 47
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 48
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 49
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 50
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 51
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 56
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 57
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 58
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 60
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 61
[16:12:58.117]     INFO:   masking Roc 0 col/row: 51 62
[16:12:58.127]     INFO:   masking Roc 1 col/row: 29 10
[16:12:58.127]     INFO:   masking Roc 1 col/row: 29 11
[16:12:58.127]     INFO:   masking Roc 1 col/row: 29 12
[16:12:58.127]     INFO:   masking Roc 1 col/row: 29 13
[16:12:58.127]     INFO:   masking Roc 1 col/row: 29 14
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 9
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 10
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 11
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 12
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 13
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 14
[16:12:58.127]     INFO:   masking Roc 1 col/row: 30 15
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 8
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 9
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 10
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 11
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 12
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 13
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 14
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 15
[16:12:58.127]     INFO:   masking Roc 1 col/row: 31 16
[16:12:58.127]     INFO:   masking Roc 1 col/row: 32 9
[16:12:58.127]     INFO:   masking Roc 1 col/row: 32 10
[16:12:58.127]     INFO:   masking Roc 1 col/row: 32 11
[16:12:58.127]     INFO:   masking Roc 1 col/row: 32 12
[16:12:58.127]     INFO:   masking Roc 1 col/row: 32 13
[16:12:58.128]     INFO:   masking Roc 1 col/row: 32 14
[16:12:58.128]     INFO:   masking Roc 1 col/row: 32 15
[16:12:58.128]     INFO:   masking Roc 1 col/row: 32 16
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 10
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 11
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 12
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 13
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 14
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 15
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 26
[16:12:58.128]     INFO:   masking Roc 1 col/row: 33 27
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 9
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 10
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 11
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 12
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 13
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 26
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 27
[16:12:58.128]     INFO:   masking Roc 1 col/row: 34 28
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 9
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 10
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 11
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 12
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 13
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 14
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 15
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 16
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 25
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 26
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 27
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 28
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 29
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 37
[16:12:58.128]     INFO:   masking Roc 1 col/row: 35 38
[16:12:58.128]     INFO:   masking Roc 1 col/row: 36 27
[16:12:58.128]     INFO:   masking Roc 1 col/row: 36 38
[16:12:58.128]     INFO:   masking Roc 1 col/row: 36 40
[16:12:58.128]     INFO:   masking Roc 1 col/row: 36 42
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 41
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 42
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 43
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 48
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 49
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 53
[16:12:58.128]     INFO:   masking Roc 1 col/row: 37 54
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 48
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 49
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 50
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 51
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 52
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 53
[16:12:58.128]     INFO:   masking Roc 1 col/row: 38 54
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 51
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 52
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 53
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 54
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 55
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 56
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 57
[16:12:58.128]     INFO:   masking Roc 1 col/row: 39 58
[16:12:58.129]     INFO:   masking Roc 1 col/row: 40 53
[16:12:58.129]     INFO:   masking Roc 1 col/row: 40 57
[16:12:58.129]     INFO:   masking Roc 1 col/row: 40 58
[16:12:58.129]     INFO:   masking Roc 1 col/row: 40 59
[16:12:58.269]     INFO:         clk: 4
[16:12:58.269]     INFO:         ctr: 4
[16:12:58.269]     INFO:         sda: 19
[16:12:58.269]     INFO:         tin: 9
[16:12:58.269]     INFO:         level: 15
[16:12:58.269]     INFO:         triggerdelay: 0
[16:12:58.269]    QUIET: Instanciating API for pxar v1.9.0+818~g9672706
[16:12:58.269]     INFO: Log level: DEBUG
[16:12:58.280]    QUIET: Connection to board DTB_WRPRHI opened.
[16:12:58.283]     INFO: DTB startup information
--- DTB info------------------------------------------
Board id:    58
HW version:  DTB1.2
FW version:  4.2
SW version:  4.5
USB id:      DTB_WRPRHI
MAC address: 40D85511803A
Hostname:    pixelDTB058
Comment:     
------------------------------------------------------
[16:12:58.286]     INFO: RPC call hashes of host and DTB match: 398089610
[16:12:59.888]     INFO: DUT info: 
[16:12:59.888]     INFO: The DUT currently contains the following objects:
[16:12:59.888]     INFO:  2 TBM Cores tbm08c (2 ON)
[16:12:59.888]     INFO: 	TBM Core alpha (0): 7 registers set
[16:12:59.888]     INFO: 	TBM Core beta  (1): 7 registers set
[16:12:59.888]     INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[16:12:59.888]     INFO: 	ROC 0: 19 DACs set, Pixels: 65 masked, 0 active.
[16:12:59.888]     INFO: 	ROC 1: 19 DACs set, Pixels: 90 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]     INFO: 	ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB<-
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB2<-
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 222
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   plwidth: 35
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB3<-
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   vcals: 250
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->BB4<-
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   savecaldelscan: checkbox(0)
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 100
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   cals: 1
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   caldello: 80
[16:12:59.889]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelhi: 200
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelstep: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomplo: 70
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcomphi: 130
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompstep: 5
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   noisypixels: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 255
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   cut: 0.5
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Cmd<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DAQ<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   trgnumber: 5
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqtrg: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   daqseconds: 5
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaqseconds: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacDacScan<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1: caldel
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1lo: 0
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac1hi: 255
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2: vthrcomp
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2lo: 0
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac2hi: 255
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->DacScan<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   phmap: checkbox(1)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   allpixels: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   unmasked: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: vcal
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 255
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->GainPedestal<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   showfits: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   extended: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   dumphists: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   vcalstep: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   measure: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   fit: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   save: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->HighRate<-
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixels: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   trimhotpixelthr: 200
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   runsecondshotpixels: 10
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   savetrimbits: checkbox(1)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   maskuntrimmable: checkbox(1)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   caldelscan: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   xpixelalive: button
[16:12:59.890]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   xnoisemaps: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 100
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: 20
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   rundaq: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 20
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 2
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   triggerdelay: 20
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->IV<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   port: /dev/FIXME
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestart: 0
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestop: 600
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   voltagestep: 5
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   delay: 1
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   compliance(ua): 100
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PhOptimization<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   safetymarginlow: 20
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   saturationvcal: 100
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   quantilesaturation: 0.98
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->PixelAlive<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 200
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   alivetest: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   masktest: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   addressdecodingtest: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Pretest<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   programroc: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   targetia: 24
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   iterations: 100
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   settimings: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   findtiming: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   findworkingpixel: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   setvthrcompcaldel: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   pix: 11,20
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 250
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   deltavthrcomp: 50
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   fraccaldel: 0.5
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 5
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   savedacs: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Readback<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   calibratevd: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateva: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   calibrateia: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   readbackvbg: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   getcalibratedvbg: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalvd: checkbox(1)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   usecalva: checkbox(0)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   setvana: button
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Scurves<-
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   adjustvcal: checkbox(0)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpall: checkbox(0)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpproblematic: checkbox(0)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dumpoutputfile: checkbox(0)
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 50
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   dac: Vcal
[16:12:59.891]    DEBUG: <PixTestParameters.cc/dump:L107>   daclo: 0
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   dachi: 200
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   dacs/step: -1
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig/step: -1
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   scurves: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Timing<-
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   targetclk: 4
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 10
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   clocksdascan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   notokenpass: checkbox(0)
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   phasescan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   levelscan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   tbmphasescan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   rocdelayscan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   timingtest: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   saveparameters: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Trim<-
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   trim: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   ntrig: 8
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   vcal: 35
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   trimbits: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L104> PixTestParameters: ->Xray<-
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   maskhotpixels: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   savemaskfile: checkbox(0)
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   maskfilename: default
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   source: Ag
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   phrun: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   runseconds: 100
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   trgfrequency(khz): 100
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   ratescan: button
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmin: 10
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   vthrcompmax: 80
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   stepseconds: 5
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   delaytbm: checkbox
[16:12:59.892]    DEBUG: <PixTestParameters.cc/dump:L107>   filltree: checkbox
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L81> PixSetup init start; getCurrentRSS() = 32727040
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L87> fPixTestParameters = 0x1c7d0b0
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L88>  fConfigParameters = 0x1a1f370
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L89>        fPxarMemory = 0x7f403bd83010
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L90>         fPxarMemHi = 0x7f4041fee510
[16:12:59.894]    DEBUG: <PixSetup.cc/init:L106> PixSetup init done;  getCurrentRSS() = 32735232 fPxarMemory = 0x7f403bd83010
[16:12:59.895]    DEBUG: <pXar.cc/main:L223> Initial Analog Current: 394.7mA
[16:12:59.897]    DEBUG: <pXar.cc/main:L224> Initial Digital Current: 471.1mA
[16:12:59.897]    DEBUG: <pXar.cc/main:L225> Initial Module Temperature: -0.4 C
[16:13:00.394]    DEBUG: <PixGui.cc/hvOn:L460> HV set On: 0x206c430
[16:13:00.456]    DEBUG: <PixTestFactory.cc/PixTestFactory:L53> PixTestFactory::PixTestFactory()
[16:13:00.456]    DEBUG: <PixTestBBMap.cc/init:L79> PixTestBBMap::init()
[16:13:00.456]    DEBUG: <PixTestBBMap.cc/PixTestBBMap:L27> PixTestBBMap ctor(PixSetup &a, string, TGTab *)
[16:13:00.462]    DEBUG: <PixTestBB2Map.cc/setParameter:L58> setting fTargetIa    = 24 mA/ROC
[16:13:00.462]    DEBUG: <PixTestBB2Map.cc/init:L97> PixTestBB2Map::init()
[16:13:00.462]    DEBUG: <PixTestBB2Map.cc/PixTestBB2Map:L29> PixTestBB2Map ctor(PixSetup &a, string, TGTab *)
[16:13:00.471]    DEBUG: <PixTestBB3Map.cc/init:L81> PixTestBB3Map::init()
[16:13:00.471]    DEBUG: <PixTestBB3Map.cc/PixTestBB3Map:L29> PixTestBB3Map ctor(PixSetup &a, string, TGTab *)
[16:13:00.479]    DEBUG: <PixTestBB4Map.cc/init:L93> PixTestBB4Map::init()
[16:13:00.479]    DEBUG: <PixTestBB4Map.cc/PixTestBB4Map:L26> PixTestMapeff ctor(PixSetup &a, string, TGTab *)
[16:13:00.502]     INFO: PixTestCmd::init()
[16:13:00.516]    DEBUG: <PixTestDaq.cc/init:L44> PixTestDaq::init()
[16:13:00.516]    DEBUG: <PixTestDaq.cc/PixTestDaq:L22> PixTestDaq ctor(PixSetup &a, string, TGTab *)
[16:13:00.516]     INFO: readGainPedestalParameters data/mp315/phCalibrationFitErr35_C0.dat .. data/mp315/phCalibrationFitErr35_C15.dat
[16:13:00.765]    DEBUG: <PixTestDacDacScan.cc/init:L103> PixTestDacDacScan::init()
[16:13:00.765]    DEBUG: <PixTestDacDacScan.cc/PixTestDacDacScan:L22> PixTestDacDacScan ctor(PixSetup &a, string, TGTab *)
[16:13:00.780]    DEBUG: <PixTestGainPedestal.cc/setParameter:L83> PixTestGainPedestal::PixTest() fVcalStep = 10
[16:13:00.787]    DEBUG: <PixTestHighRate.cc/setParameter:L68>   setting fParTriggerFrequency -> 20
[16:13:00.787]    DEBUG: <PixTestHighRate.cc/init:L211> PixTestHighRate::init()
[16:13:00.787]    DEBUG: <PixTestHighRate.cc/PixTestHighRate:L31> PixTestHighRate ctor(PixSetup &a, string, TGTab *)
[16:13:00.812]    DEBUG: <PixTest.cc/setTestParameter:L637>  setting  ntrig to new value 10
[16:13:00.813]    DEBUG: <PixTestPhOptimization.cc/setParameter:L37>   setting fParNtrig  ->10<- from sval = 10
[16:13:00.813]    DEBUG: <PixTestPhOptimization.cc/setParameter:L42>   setting fSafetyMarginLow  ->20<- from sval = 20
[16:13:00.813]    DEBUG: <PixTestPhOptimization.cc/setParameter:L48>   setting fVcalMax  ->100<- from sval = 100
[16:13:00.813]    DEBUG: <PixTestPhOptimization.cc/setParameter:L53>   setting fQuantMax  ->0.98<- from sval = 0.98
[16:13:00.830]    DEBUG: <PixTestAlive.cc/init:L83> PixTestAlive::init()
[16:13:00.830]    DEBUG: <PixTestAlive.cc/PixTestAlive:L21> PixTestAlive ctor(PixSetup &a, string, TGTab *)
[16:13:00.858]    DEBUG: <PixTestReadback.cc/setParameter:L172> fCalwVd set to 1
[16:13:00.858]    DEBUG: <PixTestReadback.cc/init:L95> PixTestReadback::init()
[16:13:00.858]    DEBUG: <PixTestReadback.cc/PixTestReadback:L22> PixTestReadback ctor(PixSetup &a, string, TGTab *)
[16:13:00.858]     INFO: readReadbackCal: data/mp315/readbackCal_C0.dat .. data/mp315/readbackCal_C15.dat
[16:13:00.876]    DEBUG: <PixTestScurves.cc/setParameter:L93> set fOutputFilename = 
[16:13:00.884]    DEBUG: <PixTestTiming.cc/setParameter:L59> PixTestTiming::PixTest() targetclk = 4
[16:13:00.884]    DEBUG: <PixTestTiming.cc/setParameter:L63> PixTestTiming::PixTest() ntrig = 10
[16:13:00.884]    DEBUG: <PixTestTiming.cc/setParameter:L47> fNoTokenPass: 0
[16:13:00.885]    DEBUG: <PixTestTiming.cc/init:L73> PixTestTiming::init()
[16:13:00.906]    DEBUG: <PixTestXray.cc/init:L135> PixTestXray::init()
[16:13:00.906]    DEBUG: <PixTestXray.cc/PixTestXray:L28> PixTestXray ctor(PixSetup &a, string, TGTab *)
[16:13:02.973]     INFO: ######################################################################
[16:13:02.973]     INFO: PixTestAlive::doTest()
[16:13:02.973]     INFO: ######################################################################
[16:13:02.976]     INFO:    ----------------------------------------------------------------------
[16:13:02.976]     INFO:    PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:13:02.976]     INFO:    ----------------------------------------------------------------------
[16:13:02.979]     INFO: ROC 0 masking pixel 50/5
[16:13:02.979]     INFO: ROC 0 masking pixel 50/6
[16:13:02.979]     INFO: ROC 0 masking pixel 50/7
[16:13:02.979]     INFO: ROC 0 masking pixel 50/8
[16:13:02.979]     INFO: ROC 0 masking pixel 50/9
[16:13:02.979]     INFO: ROC 0 masking pixel 50/10
[16:13:02.979]     INFO: ROC 0 masking pixel 50/11
[16:13:02.979]     INFO: ROC 0 masking pixel 50/12
[16:13:02.979]     INFO: ROC 0 masking pixel 50/13
[16:13:02.979]     INFO: ROC 0 masking pixel 50/15
[16:13:02.979]     INFO: ROC 0 masking pixel 51/3
[16:13:02.979]     INFO: ROC 0 masking pixel 51/4
[16:13:02.979]     INFO: ROC 0 masking pixel 51/5
[16:13:02.979]     INFO: ROC 0 masking pixel 51/6
[16:13:02.979]     INFO: ROC 0 masking pixel 51/7
[16:13:02.979]     INFO: ROC 0 masking pixel 51/8
[16:13:02.979]     INFO: ROC 0 masking pixel 51/9
[16:13:02.979]     INFO: ROC 0 masking pixel 51/10
[16:13:02.979]     INFO: ROC 0 masking pixel 51/11
[16:13:02.979]     INFO: ROC 0 masking pixel 51/12
[16:13:02.979]     INFO: ROC 0 masking pixel 51/13
[16:13:02.979]     INFO: ROC 0 masking pixel 51/14
[16:13:02.979]     INFO: ROC 0 masking pixel 51/15
[16:13:02.979]     INFO: ROC 0 masking pixel 51/16
[16:13:02.979]     INFO: ROC 0 masking pixel 51/17
[16:13:02.979]     INFO: ROC 0 masking pixel 51/18
[16:13:02.979]     INFO: ROC 0 masking pixel 51/19
[16:13:02.979]     INFO: ROC 0 masking pixel 51/20
[16:13:02.979]     INFO: ROC 0 masking pixel 51/21
[16:13:02.979]     INFO: ROC 0 masking pixel 51/22
[16:13:02.979]     INFO: ROC 0 masking pixel 51/23
[16:13:02.979]     INFO: ROC 0 masking pixel 51/24
[16:13:02.979]     INFO: ROC 0 masking pixel 51/25
[16:13:02.979]     INFO: ROC 0 masking pixel 51/26
[16:13:02.979]     INFO: ROC 0 masking pixel 51/27
[16:13:02.979]     INFO: ROC 0 masking pixel 51/28
[16:13:02.979]     INFO: ROC 0 masking pixel 51/29
[16:13:02.979]     INFO: ROC 0 masking pixel 51/30
[16:13:02.980]     INFO: ROC 0 masking pixel 51/31
[16:13:02.980]     INFO: ROC 0 masking pixel 51/32
[16:13:02.980]     INFO: ROC 0 masking pixel 51/33
[16:13:02.980]     INFO: ROC 0 masking pixel 51/34
[16:13:02.980]     INFO: ROC 0 masking pixel 51/35
[16:13:02.980]     INFO: ROC 0 masking pixel 51/36
[16:13:02.980]     INFO: ROC 0 masking pixel 51/37
[16:13:02.980]     INFO: ROC 0 masking pixel 51/38
[16:13:02.980]     INFO: ROC 0 masking pixel 51/39
[16:13:02.980]     INFO: ROC 0 masking pixel 51/40
[16:13:02.980]     INFO: ROC 0 masking pixel 51/41
[16:13:02.980]     INFO: ROC 0 masking pixel 51/42
[16:13:02.980]     INFO: ROC 0 masking pixel 51/43
[16:13:02.980]     INFO: ROC 0 masking pixel 51/44
[16:13:02.980]     INFO: ROC 0 masking pixel 51/45
[16:13:02.980]     INFO: ROC 0 masking pixel 51/46
[16:13:02.980]     INFO: ROC 0 masking pixel 51/47
[16:13:02.980]     INFO: ROC 0 masking pixel 51/48
[16:13:02.980]     INFO: ROC 0 masking pixel 51/49
[16:13:02.980]     INFO: ROC 0 masking pixel 51/50
[16:13:02.980]     INFO: ROC 0 masking pixel 51/51
[16:13:02.980]     INFO: ROC 0 masking pixel 51/56
[16:13:02.980]     INFO: ROC 0 masking pixel 51/57
[16:13:02.980]     INFO: ROC 0 masking pixel 51/58
[16:13:02.980]     INFO: ROC 0 masking pixel 51/60
[16:13:02.980]     INFO: ROC 0 masking pixel 51/61
[16:13:02.980]     INFO: ROC 0 masking pixel 51/62
[16:13:02.980]     INFO: ROC 1 masking pixel 29/10
[16:13:02.980]     INFO: ROC 1 masking pixel 29/11
[16:13:02.980]     INFO: ROC 1 masking pixel 29/12
[16:13:02.980]     INFO: ROC 1 masking pixel 29/13
[16:13:02.980]     INFO: ROC 1 masking pixel 29/14
[16:13:02.980]     INFO: ROC 1 masking pixel 30/9
[16:13:02.980]     INFO: ROC 1 masking pixel 30/10
[16:13:02.980]     INFO: ROC 1 masking pixel 30/11
[16:13:02.980]     INFO: ROC 1 masking pixel 30/12
[16:13:02.980]     INFO: ROC 1 masking pixel 30/13
[16:13:02.980]     INFO: ROC 1 masking pixel 30/14
[16:13:02.980]     INFO: ROC 1 masking pixel 30/15
[16:13:02.980]     INFO: ROC 1 masking pixel 31/8
[16:13:02.980]     INFO: ROC 1 masking pixel 31/9
[16:13:02.980]     INFO: ROC 1 masking pixel 31/10
[16:13:02.980]     INFO: ROC 1 masking pixel 31/11
[16:13:02.980]     INFO: ROC 1 masking pixel 31/12
[16:13:02.980]     INFO: ROC 1 masking pixel 31/13
[16:13:02.981]     INFO: ROC 1 masking pixel 31/14
[16:13:02.981]     INFO: ROC 1 masking pixel 31/15
[16:13:02.981]     INFO: ROC 1 masking pixel 31/16
[16:13:02.981]     INFO: ROC 1 masking pixel 32/9
[16:13:02.981]     INFO: ROC 1 masking pixel 32/10
[16:13:02.981]     INFO: ROC 1 masking pixel 32/11
[16:13:02.981]     INFO: ROC 1 masking pixel 32/12
[16:13:02.981]     INFO: ROC 1 masking pixel 32/13
[16:13:02.981]     INFO: ROC 1 masking pixel 32/14
[16:13:02.981]     INFO: ROC 1 masking pixel 32/15
[16:13:02.981]     INFO: ROC 1 masking pixel 32/16
[16:13:02.981]     INFO: ROC 1 masking pixel 33/10
[16:13:02.981]     INFO: ROC 1 masking pixel 33/11
[16:13:02.981]     INFO: ROC 1 masking pixel 33/12
[16:13:02.981]     INFO: ROC 1 masking pixel 33/13
[16:13:02.981]     INFO: ROC 1 masking pixel 33/14
[16:13:02.981]     INFO: ROC 1 masking pixel 33/15
[16:13:02.981]     INFO: ROC 1 masking pixel 33/26
[16:13:02.981]     INFO: ROC 1 masking pixel 33/27
[16:13:02.981]     INFO: ROC 1 masking pixel 34/9
[16:13:02.981]     INFO: ROC 1 masking pixel 34/10
[16:13:02.981]     INFO: ROC 1 masking pixel 34/11
[16:13:02.981]     INFO: ROC 1 masking pixel 34/12
[16:13:02.981]     INFO: ROC 1 masking pixel 34/13
[16:13:02.981]     INFO: ROC 1 masking pixel 34/26
[16:13:02.981]     INFO: ROC 1 masking pixel 34/27
[16:13:02.981]     INFO: ROC 1 masking pixel 34/28
[16:13:02.981]     INFO: ROC 1 masking pixel 35/9
[16:13:02.981]     INFO: ROC 1 masking pixel 35/10
[16:13:02.981]     INFO: ROC 1 masking pixel 35/11
[16:13:02.981]     INFO: ROC 1 masking pixel 35/12
[16:13:02.981]     INFO: ROC 1 masking pixel 35/13
[16:13:02.981]     INFO: ROC 1 masking pixel 35/14
[16:13:02.981]     INFO: ROC 1 masking pixel 35/15
[16:13:02.981]     INFO: ROC 1 masking pixel 35/16
[16:13:02.981]     INFO: ROC 1 masking pixel 35/25
[16:13:02.981]     INFO: ROC 1 masking pixel 35/26
[16:13:02.981]     INFO: ROC 1 masking pixel 35/27
[16:13:02.981]     INFO: ROC 1 masking pixel 35/28
[16:13:02.981]     INFO: ROC 1 masking pixel 35/29
[16:13:02.981]     INFO: ROC 1 masking pixel 35/37
[16:13:02.981]     INFO: ROC 1 masking pixel 35/38
[16:13:02.981]     INFO: ROC 1 masking pixel 36/27
[16:13:02.981]     INFO: ROC 1 masking pixel 36/38
[16:13:02.981]     INFO: ROC 1 masking pixel 36/40
[16:13:02.981]     INFO: ROC 1 masking pixel 36/42
[16:13:02.981]     INFO: ROC 1 masking pixel 37/41
[16:13:02.981]     INFO: ROC 1 masking pixel 37/42
[16:13:02.981]     INFO: ROC 1 masking pixel 37/43
[16:13:02.982]     INFO: ROC 1 masking pixel 37/48
[16:13:02.982]     INFO: ROC 1 masking pixel 37/49
[16:13:02.982]     INFO: ROC 1 masking pixel 37/53
[16:13:02.982]     INFO: ROC 1 masking pixel 37/54
[16:13:02.982]     INFO: ROC 1 masking pixel 38/48
[16:13:02.982]     INFO: ROC 1 masking pixel 38/49
[16:13:02.982]     INFO: ROC 1 masking pixel 38/50
[16:13:02.982]     INFO: ROC 1 masking pixel 38/51
[16:13:02.982]     INFO: ROC 1 masking pixel 38/52
[16:13:02.982]     INFO: ROC 1 masking pixel 38/53
[16:13:02.982]     INFO: ROC 1 masking pixel 38/54
[16:13:02.982]     INFO: ROC 1 masking pixel 39/51
[16:13:02.982]     INFO: ROC 1 masking pixel 39/52
[16:13:02.982]     INFO: ROC 1 masking pixel 39/53
[16:13:02.982]     INFO: ROC 1 masking pixel 39/54
[16:13:02.982]     INFO: ROC 1 masking pixel 39/55
[16:13:02.982]     INFO: ROC 1 masking pixel 39/56
[16:13:02.982]     INFO: ROC 1 masking pixel 39/57
[16:13:02.982]     INFO: ROC 1 masking pixel 39/58
[16:13:02.982]     INFO: ROC 1 masking pixel 40/53
[16:13:02.982]     INFO: ROC 1 masking pixel 40/57
[16:13:02.982]     INFO: ROC 1 masking pixel 40/58
[16:13:02.982]     INFO: ROC 1 masking pixel 40/59
[16:13:02.982]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:03.361]     INFO: Expecting 41600 events.
[16:13:07.750]     INFO: 41600 events read in total (3670ms).
[16:13:07.898]     INFO: Test took 4916ms.
[16:13:07.910]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:07.910]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66401
[16:13:07.910]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists PixelAlive_C0 .. PixelAlive_C15
[16:13:08.202]     INFO: PixTestAlive::aliveTest() done
[16:13:08.202]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    1    3    0    0    0    0    0    0    0
[16:13:08.202]    DEBUG: <PixTestAlive.cc/aliveTest:L199> number of red-efficiency pixels:    90   96   42   61   66   79   73   58   77   71   59   67   75   50   23   33
[16:13:08.203]     INFO: ROC 0 masking pixel 50/5
[16:13:08.203]     INFO: ROC 0 masking pixel 50/6
[16:13:08.203]     INFO: ROC 0 masking pixel 50/7
[16:13:08.203]     INFO: ROC 0 masking pixel 50/8
[16:13:08.203]     INFO: ROC 0 masking pixel 50/9
[16:13:08.203]     INFO: ROC 0 masking pixel 50/10
[16:13:08.203]     INFO: ROC 0 masking pixel 50/11
[16:13:08.203]     INFO: ROC 0 masking pixel 50/12
[16:13:08.203]     INFO: ROC 0 masking pixel 50/13
[16:13:08.203]     INFO: ROC 0 masking pixel 50/15
[16:13:08.203]     INFO: ROC 0 masking pixel 51/3
[16:13:08.203]     INFO: ROC 0 masking pixel 51/4
[16:13:08.203]     INFO: ROC 0 masking pixel 51/5
[16:13:08.203]     INFO: ROC 0 masking pixel 51/6
[16:13:08.203]     INFO: ROC 0 masking pixel 51/7
[16:13:08.203]     INFO: ROC 0 masking pixel 51/8
[16:13:08.203]     INFO: ROC 0 masking pixel 51/9
[16:13:08.203]     INFO: ROC 0 masking pixel 51/10
[16:13:08.203]     INFO: ROC 0 masking pixel 51/11
[16:13:08.203]     INFO: ROC 0 masking pixel 51/12
[16:13:08.203]     INFO: ROC 0 masking pixel 51/13
[16:13:08.203]     INFO: ROC 0 masking pixel 51/14
[16:13:08.203]     INFO: ROC 0 masking pixel 51/15
[16:13:08.203]     INFO: ROC 0 masking pixel 51/16
[16:13:08.203]     INFO: ROC 0 masking pixel 51/17
[16:13:08.203]     INFO: ROC 0 masking pixel 51/18
[16:13:08.203]     INFO: ROC 0 masking pixel 51/19
[16:13:08.203]     INFO: ROC 0 masking pixel 51/20
[16:13:08.203]     INFO: ROC 0 masking pixel 51/21
[16:13:08.203]     INFO: ROC 0 masking pixel 51/22
[16:13:08.203]     INFO: ROC 0 masking pixel 51/23
[16:13:08.203]     INFO: ROC 0 masking pixel 51/24
[16:13:08.203]     INFO: ROC 0 masking pixel 51/25
[16:13:08.203]     INFO: ROC 0 masking pixel 51/26
[16:13:08.203]     INFO: ROC 0 masking pixel 51/27
[16:13:08.203]     INFO: ROC 0 masking pixel 51/28
[16:13:08.203]     INFO: ROC 0 masking pixel 51/29
[16:13:08.203]     INFO: ROC 0 masking pixel 51/30
[16:13:08.203]     INFO: ROC 0 masking pixel 51/31
[16:13:08.203]     INFO: ROC 0 masking pixel 51/32
[16:13:08.203]     INFO: ROC 0 masking pixel 51/33
[16:13:08.203]     INFO: ROC 0 masking pixel 51/34
[16:13:08.203]     INFO: ROC 0 masking pixel 51/35
[16:13:08.203]     INFO: ROC 0 masking pixel 51/36
[16:13:08.203]     INFO: ROC 0 masking pixel 51/37
[16:13:08.203]     INFO: ROC 0 masking pixel 51/38
[16:13:08.203]     INFO: ROC 0 masking pixel 51/39
[16:13:08.203]     INFO: ROC 0 masking pixel 51/40
[16:13:08.203]     INFO: ROC 0 masking pixel 51/41
[16:13:08.203]     INFO: ROC 0 masking pixel 51/42
[16:13:08.203]     INFO: ROC 0 masking pixel 51/43
[16:13:08.203]     INFO: ROC 0 masking pixel 51/44
[16:13:08.203]     INFO: ROC 0 masking pixel 51/45
[16:13:08.203]     INFO: ROC 0 masking pixel 51/46
[16:13:08.203]     INFO: ROC 0 masking pixel 51/47
[16:13:08.203]     INFO: ROC 0 masking pixel 51/48
[16:13:08.203]     INFO: ROC 0 masking pixel 51/49
[16:13:08.203]     INFO: ROC 0 masking pixel 51/50
[16:13:08.204]     INFO: ROC 0 masking pixel 51/51
[16:13:08.204]     INFO: ROC 0 masking pixel 51/56
[16:13:08.204]     INFO: ROC 0 masking pixel 51/57
[16:13:08.204]     INFO: ROC 0 masking pixel 51/58
[16:13:08.204]     INFO: ROC 0 masking pixel 51/60
[16:13:08.204]     INFO: ROC 0 masking pixel 51/61
[16:13:08.204]     INFO: ROC 0 masking pixel 51/62
[16:13:08.204]     INFO: ROC 1 masking pixel 29/10
[16:13:08.204]     INFO: ROC 1 masking pixel 29/11
[16:13:08.204]     INFO: ROC 1 masking pixel 29/12
[16:13:08.204]     INFO: ROC 1 masking pixel 29/13
[16:13:08.204]     INFO: ROC 1 masking pixel 29/14
[16:13:08.204]     INFO: ROC 1 masking pixel 30/9
[16:13:08.204]     INFO: ROC 1 masking pixel 30/10
[16:13:08.204]     INFO: ROC 1 masking pixel 30/11
[16:13:08.204]     INFO: ROC 1 masking pixel 30/12
[16:13:08.204]     INFO: ROC 1 masking pixel 30/13
[16:13:08.204]     INFO: ROC 1 masking pixel 30/14
[16:13:08.204]     INFO: ROC 1 masking pixel 30/15
[16:13:08.204]     INFO: ROC 1 masking pixel 31/8
[16:13:08.204]     INFO: ROC 1 masking pixel 31/9
[16:13:08.204]     INFO: ROC 1 masking pixel 31/10
[16:13:08.204]     INFO: ROC 1 masking pixel 31/11
[16:13:08.204]     INFO: ROC 1 masking pixel 31/12
[16:13:08.204]     INFO: ROC 1 masking pixel 31/13
[16:13:08.204]     INFO: ROC 1 masking pixel 31/14
[16:13:08.204]     INFO: ROC 1 masking pixel 31/15
[16:13:08.204]     INFO: ROC 1 masking pixel 31/16
[16:13:08.204]     INFO: ROC 1 masking pixel 32/9
[16:13:08.204]     INFO: ROC 1 masking pixel 32/10
[16:13:08.204]     INFO: ROC 1 masking pixel 32/11
[16:13:08.204]     INFO: ROC 1 masking pixel 32/12
[16:13:08.204]     INFO: ROC 1 masking pixel 32/13
[16:13:08.204]     INFO: ROC 1 masking pixel 32/14
[16:13:08.204]     INFO: ROC 1 masking pixel 32/15
[16:13:08.204]     INFO: ROC 1 masking pixel 32/16
[16:13:08.204]     INFO: ROC 1 masking pixel 33/10
[16:13:08.204]     INFO: ROC 1 masking pixel 33/11
[16:13:08.204]     INFO: ROC 1 masking pixel 33/12
[16:13:08.204]     INFO: ROC 1 masking pixel 33/13
[16:13:08.204]     INFO: ROC 1 masking pixel 33/14
[16:13:08.204]     INFO: ROC 1 masking pixel 33/15
[16:13:08.204]     INFO: ROC 1 masking pixel 33/26
[16:13:08.204]     INFO: ROC 1 masking pixel 33/27
[16:13:08.204]     INFO: ROC 1 masking pixel 34/9
[16:13:08.204]     INFO: ROC 1 masking pixel 34/10
[16:13:08.204]     INFO: ROC 1 masking pixel 34/11
[16:13:08.204]     INFO: ROC 1 masking pixel 34/12
[16:13:08.204]     INFO: ROC 1 masking pixel 34/13
[16:13:08.204]     INFO: ROC 1 masking pixel 34/26
[16:13:08.204]     INFO: ROC 1 masking pixel 34/27
[16:13:08.204]     INFO: ROC 1 masking pixel 34/28
[16:13:08.204]     INFO: ROC 1 masking pixel 35/9
[16:13:08.204]     INFO: ROC 1 masking pixel 35/10
[16:13:08.204]     INFO: ROC 1 masking pixel 35/11
[16:13:08.204]     INFO: ROC 1 masking pixel 35/12
[16:13:08.204]     INFO: ROC 1 masking pixel 35/13
[16:13:08.204]     INFO: ROC 1 masking pixel 35/14
[16:13:08.204]     INFO: ROC 1 masking pixel 35/15
[16:13:08.204]     INFO: ROC 1 masking pixel 35/16
[16:13:08.204]     INFO: ROC 1 masking pixel 35/25
[16:13:08.204]     INFO: ROC 1 masking pixel 35/26
[16:13:08.204]     INFO: ROC 1 masking pixel 35/27
[16:13:08.204]     INFO: ROC 1 masking pixel 35/28
[16:13:08.204]     INFO: ROC 1 masking pixel 35/29
[16:13:08.205]     INFO: ROC 1 masking pixel 35/37
[16:13:08.205]     INFO: ROC 1 masking pixel 35/38
[16:13:08.205]     INFO: ROC 1 masking pixel 36/27
[16:13:08.205]     INFO: ROC 1 masking pixel 36/38
[16:13:08.205]     INFO: ROC 1 masking pixel 36/40
[16:13:08.205]     INFO: ROC 1 masking pixel 36/42
[16:13:08.205]     INFO: ROC 1 masking pixel 37/41
[16:13:08.205]     INFO: ROC 1 masking pixel 37/42
[16:13:08.205]     INFO: ROC 1 masking pixel 37/43
[16:13:08.205]     INFO: ROC 1 masking pixel 37/48
[16:13:08.205]     INFO: ROC 1 masking pixel 37/49
[16:13:08.205]     INFO: ROC 1 masking pixel 37/53
[16:13:08.205]     INFO: ROC 1 masking pixel 37/54
[16:13:08.205]     INFO: ROC 1 masking pixel 38/48
[16:13:08.205]     INFO: ROC 1 masking pixel 38/49
[16:13:08.205]     INFO: ROC 1 masking pixel 38/50
[16:13:08.205]     INFO: ROC 1 masking pixel 38/51
[16:13:08.205]     INFO: ROC 1 masking pixel 38/52
[16:13:08.205]     INFO: ROC 1 masking pixel 38/53
[16:13:08.205]     INFO: ROC 1 masking pixel 38/54
[16:13:08.205]     INFO: ROC 1 masking pixel 39/51
[16:13:08.205]     INFO: ROC 1 masking pixel 39/52
[16:13:08.205]     INFO: ROC 1 masking pixel 39/53
[16:13:08.205]     INFO: ROC 1 masking pixel 39/54
[16:13:08.205]     INFO: ROC 1 masking pixel 39/55
[16:13:08.205]     INFO: ROC 1 masking pixel 39/56
[16:13:08.205]     INFO: ROC 1 masking pixel 39/57
[16:13:08.205]     INFO: ROC 1 masking pixel 39/58
[16:13:08.205]     INFO: ROC 1 masking pixel 40/53
[16:13:08.205]     INFO: ROC 1 masking pixel 40/57
[16:13:08.205]     INFO: ROC 1 masking pixel 40/58
[16:13:08.205]     INFO: ROC 1 masking pixel 40/59
[16:13:08.300]     INFO:    ----------------------------------------------------------------------
[16:13:08.300]     INFO:    PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:13:08.300]     INFO:    ----------------------------------------------------------------------
[16:13:08.302]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:08.679]     INFO: Expecting 41600 events.
[16:13:11.813]     INFO: 41600 events read in total (2418ms).
[16:13:11.813]     INFO: Test took 3511ms.
[16:13:11.813]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:11.814]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 0
[16:13:11.814]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists MaskTest_C0 .. MaskTest_C15
[16:13:11.814]     INFO: ROC 0 masking pixel 50/5
[16:13:11.814]     INFO: ROC 0 masking pixel 50/6
[16:13:11.814]     INFO: ROC 0 masking pixel 50/7
[16:13:11.814]     INFO: ROC 0 masking pixel 50/8
[16:13:11.814]     INFO: ROC 0 masking pixel 50/9
[16:13:11.814]     INFO: ROC 0 masking pixel 50/10
[16:13:11.814]     INFO: ROC 0 masking pixel 50/11
[16:13:11.814]     INFO: ROC 0 masking pixel 50/12
[16:13:11.814]     INFO: ROC 0 masking pixel 50/13
[16:13:11.814]     INFO: ROC 0 masking pixel 50/15
[16:13:11.814]     INFO: ROC 0 masking pixel 51/3
[16:13:11.814]     INFO: ROC 0 masking pixel 51/4
[16:13:11.814]     INFO: ROC 0 masking pixel 51/5
[16:13:11.814]     INFO: ROC 0 masking pixel 51/6
[16:13:11.814]     INFO: ROC 0 masking pixel 51/7
[16:13:11.814]     INFO: ROC 0 masking pixel 51/8
[16:13:11.814]     INFO: ROC 0 masking pixel 51/9
[16:13:11.814]     INFO: ROC 0 masking pixel 51/10
[16:13:11.814]     INFO: ROC 0 masking pixel 51/11
[16:13:11.814]     INFO: ROC 0 masking pixel 51/12
[16:13:11.814]     INFO: ROC 0 masking pixel 51/13
[16:13:11.815]     INFO: ROC 0 masking pixel 51/14
[16:13:11.815]     INFO: ROC 0 masking pixel 51/15
[16:13:11.815]     INFO: ROC 0 masking pixel 51/16
[16:13:11.815]     INFO: ROC 0 masking pixel 51/17
[16:13:11.815]     INFO: ROC 0 masking pixel 51/18
[16:13:11.815]     INFO: ROC 0 masking pixel 51/19
[16:13:11.815]     INFO: ROC 0 masking pixel 51/20
[16:13:11.815]     INFO: ROC 0 masking pixel 51/21
[16:13:11.815]     INFO: ROC 0 masking pixel 51/22
[16:13:11.815]     INFO: ROC 0 masking pixel 51/23
[16:13:11.815]     INFO: ROC 0 masking pixel 51/24
[16:13:11.815]     INFO: ROC 0 masking pixel 51/25
[16:13:11.815]     INFO: ROC 0 masking pixel 51/26
[16:13:11.815]     INFO: ROC 0 masking pixel 51/27
[16:13:11.815]     INFO: ROC 0 masking pixel 51/28
[16:13:11.815]     INFO: ROC 0 masking pixel 51/29
[16:13:11.815]     INFO: ROC 0 masking pixel 51/30
[16:13:11.815]     INFO: ROC 0 masking pixel 51/31
[16:13:11.815]     INFO: ROC 0 masking pixel 51/32
[16:13:11.815]     INFO: ROC 0 masking pixel 51/33
[16:13:11.815]     INFO: ROC 0 masking pixel 51/34
[16:13:11.815]     INFO: ROC 0 masking pixel 51/35
[16:13:11.815]     INFO: ROC 0 masking pixel 51/36
[16:13:11.815]     INFO: ROC 0 masking pixel 51/37
[16:13:11.815]     INFO: ROC 0 masking pixel 51/38
[16:13:11.815]     INFO: ROC 0 masking pixel 51/39
[16:13:11.815]     INFO: ROC 0 masking pixel 51/40
[16:13:11.815]     INFO: ROC 0 masking pixel 51/41
[16:13:11.815]     INFO: ROC 0 masking pixel 51/42
[16:13:11.815]     INFO: ROC 0 masking pixel 51/43
[16:13:11.815]     INFO: ROC 0 masking pixel 51/44
[16:13:11.815]     INFO: ROC 0 masking pixel 51/45
[16:13:11.815]     INFO: ROC 0 masking pixel 51/46
[16:13:11.815]     INFO: ROC 0 masking pixel 51/47
[16:13:11.815]     INFO: ROC 0 masking pixel 51/48
[16:13:11.815]     INFO: ROC 0 masking pixel 51/49
[16:13:11.815]     INFO: ROC 0 masking pixel 51/50
[16:13:11.815]     INFO: ROC 0 masking pixel 51/51
[16:13:11.815]     INFO: ROC 0 masking pixel 51/56
[16:13:11.815]     INFO: ROC 0 masking pixel 51/57
[16:13:11.815]     INFO: ROC 0 masking pixel 51/58
[16:13:11.815]     INFO: ROC 0 masking pixel 51/60
[16:13:11.815]     INFO: ROC 0 masking pixel 51/61
[16:13:11.815]     INFO: ROC 0 masking pixel 51/62
[16:13:11.815]     INFO: ROC 1 masking pixel 29/10
[16:13:11.816]     INFO: ROC 1 masking pixel 29/11
[16:13:11.816]     INFO: ROC 1 masking pixel 29/12
[16:13:11.816]     INFO: ROC 1 masking pixel 29/13
[16:13:11.816]     INFO: ROC 1 masking pixel 29/14
[16:13:11.816]     INFO: ROC 1 masking pixel 30/9
[16:13:11.816]     INFO: ROC 1 masking pixel 30/10
[16:13:11.816]     INFO: ROC 1 masking pixel 30/11
[16:13:11.816]     INFO: ROC 1 masking pixel 30/12
[16:13:11.816]     INFO: ROC 1 masking pixel 30/13
[16:13:11.816]     INFO: ROC 1 masking pixel 30/14
[16:13:11.816]     INFO: ROC 1 masking pixel 30/15
[16:13:11.816]     INFO: ROC 1 masking pixel 31/8
[16:13:11.816]     INFO: ROC 1 masking pixel 31/9
[16:13:11.816]     INFO: ROC 1 masking pixel 31/10
[16:13:11.816]     INFO: ROC 1 masking pixel 31/11
[16:13:11.816]     INFO: ROC 1 masking pixel 31/12
[16:13:11.816]     INFO: ROC 1 masking pixel 31/13
[16:13:11.816]     INFO: ROC 1 masking pixel 31/14
[16:13:11.816]     INFO: ROC 1 masking pixel 31/15
[16:13:11.816]     INFO: ROC 1 masking pixel 31/16
[16:13:11.816]     INFO: ROC 1 masking pixel 32/9
[16:13:11.816]     INFO: ROC 1 masking pixel 32/10
[16:13:11.816]     INFO: ROC 1 masking pixel 32/11
[16:13:11.816]     INFO: ROC 1 masking pixel 32/12
[16:13:11.816]     INFO: ROC 1 masking pixel 32/13
[16:13:11.816]     INFO: ROC 1 masking pixel 32/14
[16:13:11.816]     INFO: ROC 1 masking pixel 32/15
[16:13:11.816]     INFO: ROC 1 masking pixel 32/16
[16:13:11.816]     INFO: ROC 1 masking pixel 33/10
[16:13:11.816]     INFO: ROC 1 masking pixel 33/11
[16:13:11.816]     INFO: ROC 1 masking pixel 33/12
[16:13:11.816]     INFO: ROC 1 masking pixel 33/13
[16:13:11.816]     INFO: ROC 1 masking pixel 33/14
[16:13:11.816]     INFO: ROC 1 masking pixel 33/15
[16:13:11.816]     INFO: ROC 1 masking pixel 33/26
[16:13:11.816]     INFO: ROC 1 masking pixel 33/27
[16:13:11.816]     INFO: ROC 1 masking pixel 34/9
[16:13:11.816]     INFO: ROC 1 masking pixel 34/10
[16:13:11.816]     INFO: ROC 1 masking pixel 34/11
[16:13:11.816]     INFO: ROC 1 masking pixel 34/12
[16:13:11.816]     INFO: ROC 1 masking pixel 34/13
[16:13:11.816]     INFO: ROC 1 masking pixel 34/26
[16:13:11.816]     INFO: ROC 1 masking pixel 34/27
[16:13:11.816]     INFO: ROC 1 masking pixel 34/28
[16:13:11.816]     INFO: ROC 1 masking pixel 35/9
[16:13:11.816]     INFO: ROC 1 masking pixel 35/10
[16:13:11.816]     INFO: ROC 1 masking pixel 35/11
[16:13:11.816]     INFO: ROC 1 masking pixel 35/12
[16:13:11.816]     INFO: ROC 1 masking pixel 35/13
[16:13:11.816]     INFO: ROC 1 masking pixel 35/14
[16:13:11.817]     INFO: ROC 1 masking pixel 35/15
[16:13:11.817]     INFO: ROC 1 masking pixel 35/16
[16:13:11.817]     INFO: ROC 1 masking pixel 35/25
[16:13:11.817]     INFO: ROC 1 masking pixel 35/26
[16:13:11.817]     INFO: ROC 1 masking pixel 35/27
[16:13:11.817]     INFO: ROC 1 masking pixel 35/28
[16:13:11.817]     INFO: ROC 1 masking pixel 35/29
[16:13:11.817]     INFO: ROC 1 masking pixel 35/37
[16:13:11.817]     INFO: ROC 1 masking pixel 35/38
[16:13:11.817]     INFO: ROC 1 masking pixel 36/27
[16:13:11.817]     INFO: ROC 1 masking pixel 36/38
[16:13:11.817]     INFO: ROC 1 masking pixel 36/40
[16:13:11.817]     INFO: ROC 1 masking pixel 36/42
[16:13:11.817]     INFO: ROC 1 masking pixel 37/41
[16:13:11.817]     INFO: ROC 1 masking pixel 37/42
[16:13:11.817]     INFO: ROC 1 masking pixel 37/43
[16:13:11.817]     INFO: ROC 1 masking pixel 37/48
[16:13:11.817]     INFO: ROC 1 masking pixel 37/49
[16:13:11.817]     INFO: ROC 1 masking pixel 37/53
[16:13:11.817]     INFO: ROC 1 masking pixel 37/54
[16:13:11.817]     INFO: ROC 1 masking pixel 38/48
[16:13:11.817]     INFO: ROC 1 masking pixel 38/49
[16:13:11.817]     INFO: ROC 1 masking pixel 38/50
[16:13:11.817]     INFO: ROC 1 masking pixel 38/51
[16:13:11.817]     INFO: ROC 1 masking pixel 38/52
[16:13:11.817]     INFO: ROC 1 masking pixel 38/53
[16:13:11.817]     INFO: ROC 1 masking pixel 38/54
[16:13:11.817]     INFO: ROC 1 masking pixel 39/51
[16:13:11.817]     INFO: ROC 1 masking pixel 39/52
[16:13:11.817]     INFO: ROC 1 masking pixel 39/53
[16:13:11.817]     INFO: ROC 1 masking pixel 39/54
[16:13:11.817]     INFO: ROC 1 masking pixel 39/55
[16:13:11.817]     INFO: ROC 1 masking pixel 39/56
[16:13:11.817]     INFO: ROC 1 masking pixel 39/57
[16:13:11.817]     INFO: ROC 1 masking pixel 39/58
[16:13:11.817]     INFO: ROC 1 masking pixel 40/53
[16:13:11.817]     INFO: ROC 1 masking pixel 40/57
[16:13:11.817]     INFO: ROC 1 masking pixel 40/58
[16:13:11.817]     INFO: ROC 1 masking pixel 40/59
[16:13:11.817]     INFO: mask vs. old pixelAlive PixelAlive_C0_V0 ..  PixelAlive_C15_V0
[16:13:12.236]     INFO: PixTestAlive::maskTest() done
[16:13:12.236]     INFO: number of mask-defect pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:13:12.236]     INFO: ROC 0 masking pixel 50/5
[16:13:12.236]     INFO: ROC 0 masking pixel 50/6
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[16:13:12.261]     INFO:    ----------------------------------------------------------------------
[16:13:12.261]     INFO:    PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[16:13:12.261]     INFO:    ----------------------------------------------------------------------
[16:13:12.263]     INFO: ROC 0 masking pixel 50/5
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[16:13:12.266]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:12.644]     INFO: Expecting 41600 events.
[16:13:17.046]     INFO: 41600 events read in total (3687ms).
[16:13:17.047]     INFO: Test took 4781ms.
[16:13:17.056]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:17.057]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 66405
[16:13:17.057]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists AddressDecodingTest_C0 .. AddressDecodingTest_C15
[16:13:17.425]     INFO: PixTestAlive::addressDecodingTest() done
[16:13:17.425]     INFO: number of address-decoding pixels (per ROC):     0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:13:17.425]     INFO: ROC 0 masking pixel 50/5
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[16:13:17.427]     INFO: ROC 0 masking pixel 51/62
[16:13:17.427]     INFO: ROC 1 masking pixel 29/10
[16:13:17.427]     INFO: ROC 1 masking pixel 29/11
[16:13:17.427]     INFO: ROC 1 masking pixel 29/12
[16:13:17.427]     INFO: ROC 1 masking pixel 29/13
[16:13:17.427]     INFO: ROC 1 masking pixel 29/14
[16:13:17.427]     INFO: ROC 1 masking pixel 30/9
[16:13:17.427]     INFO: ROC 1 masking pixel 30/10
[16:13:17.427]     INFO: ROC 1 masking pixel 30/11
[16:13:17.427]     INFO: ROC 1 masking pixel 30/12
[16:13:17.427]     INFO: ROC 1 masking pixel 30/13
[16:13:17.427]     INFO: ROC 1 masking pixel 30/14
[16:13:17.427]     INFO: ROC 1 masking pixel 30/15
[16:13:17.427]     INFO: ROC 1 masking pixel 31/8
[16:13:17.427]     INFO: ROC 1 masking pixel 31/9
[16:13:17.427]     INFO: ROC 1 masking pixel 31/10
[16:13:17.427]     INFO: ROC 1 masking pixel 31/11
[16:13:17.427]     INFO: ROC 1 masking pixel 31/12
[16:13:17.427]     INFO: ROC 1 masking pixel 31/13
[16:13:17.427]     INFO: ROC 1 masking pixel 31/14
[16:13:17.427]     INFO: ROC 1 masking pixel 31/15
[16:13:17.427]     INFO: ROC 1 masking pixel 31/16
[16:13:17.427]     INFO: ROC 1 masking pixel 32/9
[16:13:17.427]     INFO: ROC 1 masking pixel 32/10
[16:13:17.427]     INFO: ROC 1 masking pixel 32/11
[16:13:17.427]     INFO: ROC 1 masking pixel 32/12
[16:13:17.427]     INFO: ROC 1 masking pixel 32/13
[16:13:17.427]     INFO: ROC 1 masking pixel 32/14
[16:13:17.427]     INFO: ROC 1 masking pixel 32/15
[16:13:17.427]     INFO: ROC 1 masking pixel 32/16
[16:13:17.427]     INFO: ROC 1 masking pixel 33/10
[16:13:17.427]     INFO: ROC 1 masking pixel 33/11
[16:13:17.427]     INFO: ROC 1 masking pixel 33/12
[16:13:17.427]     INFO: ROC 1 masking pixel 33/13
[16:13:17.427]     INFO: ROC 1 masking pixel 33/14
[16:13:17.427]     INFO: ROC 1 masking pixel 33/15
[16:13:17.427]     INFO: ROC 1 masking pixel 33/26
[16:13:17.427]     INFO: ROC 1 masking pixel 33/27
[16:13:17.427]     INFO: ROC 1 masking pixel 34/9
[16:13:17.427]     INFO: ROC 1 masking pixel 34/10
[16:13:17.427]     INFO: ROC 1 masking pixel 34/11
[16:13:17.428]     INFO: ROC 1 masking pixel 34/12
[16:13:17.428]     INFO: ROC 1 masking pixel 34/13
[16:13:17.428]     INFO: ROC 1 masking pixel 34/26
[16:13:17.428]     INFO: ROC 1 masking pixel 34/27
[16:13:17.428]     INFO: ROC 1 masking pixel 34/28
[16:13:17.428]     INFO: ROC 1 masking pixel 35/9
[16:13:17.428]     INFO: ROC 1 masking pixel 35/10
[16:13:17.428]     INFO: ROC 1 masking pixel 35/11
[16:13:17.428]     INFO: ROC 1 masking pixel 35/12
[16:13:17.428]     INFO: ROC 1 masking pixel 35/13
[16:13:17.428]     INFO: ROC 1 masking pixel 35/14
[16:13:17.428]     INFO: ROC 1 masking pixel 35/15
[16:13:17.428]     INFO: ROC 1 masking pixel 35/16
[16:13:17.428]     INFO: ROC 1 masking pixel 35/25
[16:13:17.428]     INFO: ROC 1 masking pixel 35/26
[16:13:17.428]     INFO: ROC 1 masking pixel 35/27
[16:13:17.428]     INFO: ROC 1 masking pixel 35/28
[16:13:17.428]     INFO: ROC 1 masking pixel 35/29
[16:13:17.428]     INFO: ROC 1 masking pixel 35/37
[16:13:17.428]     INFO: ROC 1 masking pixel 35/38
[16:13:17.428]     INFO: ROC 1 masking pixel 36/27
[16:13:17.428]     INFO: ROC 1 masking pixel 36/38
[16:13:17.428]     INFO: ROC 1 masking pixel 36/40
[16:13:17.428]     INFO: ROC 1 masking pixel 36/42
[16:13:17.428]     INFO: ROC 1 masking pixel 37/41
[16:13:17.428]     INFO: ROC 1 masking pixel 37/42
[16:13:17.428]     INFO: ROC 1 masking pixel 37/43
[16:13:17.428]     INFO: ROC 1 masking pixel 37/48
[16:13:17.428]     INFO: ROC 1 masking pixel 37/49
[16:13:17.428]     INFO: ROC 1 masking pixel 37/53
[16:13:17.428]     INFO: ROC 1 masking pixel 37/54
[16:13:17.428]     INFO: ROC 1 masking pixel 38/48
[16:13:17.428]     INFO: ROC 1 masking pixel 38/49
[16:13:17.428]     INFO: ROC 1 masking pixel 38/50
[16:13:17.428]     INFO: ROC 1 masking pixel 38/51
[16:13:17.428]     INFO: ROC 1 masking pixel 38/52
[16:13:17.428]     INFO: ROC 1 masking pixel 38/53
[16:13:17.428]     INFO: ROC 1 masking pixel 38/54
[16:13:17.428]     INFO: ROC 1 masking pixel 39/51
[16:13:17.428]     INFO: ROC 1 masking pixel 39/52
[16:13:17.428]     INFO: ROC 1 masking pixel 39/53
[16:13:17.428]     INFO: ROC 1 masking pixel 39/54
[16:13:17.428]     INFO: ROC 1 masking pixel 39/55
[16:13:17.428]     INFO: ROC 1 masking pixel 39/56
[16:13:17.428]     INFO: ROC 1 masking pixel 39/57
[16:13:17.428]     INFO: ROC 1 masking pixel 39/58
[16:13:17.428]     INFO: ROC 1 masking pixel 40/53
[16:13:17.428]     INFO: ROC 1 masking pixel 40/57
[16:13:17.428]     INFO: ROC 1 masking pixel 40/58
[16:13:17.429]     INFO: ROC 1 masking pixel 40/59
[16:13:17.429]     INFO: PixTestAlive::doTest() done, duration: 14 seconds
[16:13:28.106]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  caldelscan
[16:13:28.106]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: caldelscan
[16:13:28.106]     INFO:    ----------------------------------------------------------------------
[16:13:28.106]     INFO:    PixTestHighRate::calDelScan() ntrig = 10, vcal = 200
[16:13:28.106]     INFO:    ----------------------------------------------------------------------
[16:13:28.245]     INFO: Expecting 768 events.
[16:13:29.378]     INFO: 768 events read in total (418ms).
[16:13:29.378]     INFO: Test took 1266ms.
[16:13:29.381]     INFO: ROC 0 masking pixel 50/5
[16:13:29.381]     INFO: ROC 0 masking pixel 50/6
[16:13:29.381]     INFO: ROC 0 masking pixel 50/7
[16:13:29.381]     INFO: ROC 0 masking pixel 50/8
[16:13:29.381]     INFO: ROC 0 masking pixel 50/9
[16:13:29.381]     INFO: ROC 0 masking pixel 50/10
[16:13:29.381]     INFO: ROC 0 masking pixel 50/11
[16:13:29.381]     INFO: ROC 0 masking pixel 50/12
[16:13:29.381]     INFO: ROC 0 masking pixel 50/13
[16:13:29.382]     INFO: ROC 0 masking pixel 50/15
[16:13:29.382]     INFO: ROC 0 masking pixel 51/3
[16:13:29.382]     INFO: ROC 0 masking pixel 51/4
[16:13:29.382]     INFO: ROC 0 masking pixel 51/5
[16:13:29.382]     INFO: ROC 0 masking pixel 51/6
[16:13:29.382]     INFO: ROC 0 masking pixel 51/7
[16:13:29.382]     INFO: ROC 0 masking pixel 51/8
[16:13:29.382]     INFO: ROC 0 masking pixel 51/9
[16:13:29.382]     INFO: ROC 0 masking pixel 51/10
[16:13:29.382]     INFO: ROC 0 masking pixel 51/11
[16:13:29.382]     INFO: ROC 0 masking pixel 51/12
[16:13:29.382]     INFO: ROC 0 masking pixel 51/13
[16:13:29.382]     INFO: ROC 0 masking pixel 51/14
[16:13:29.382]     INFO: ROC 0 masking pixel 51/15
[16:13:29.382]     INFO: ROC 0 masking pixel 51/16
[16:13:29.382]     INFO: ROC 0 masking pixel 51/17
[16:13:29.382]     INFO: ROC 0 masking pixel 51/18
[16:13:29.382]     INFO: ROC 0 masking pixel 51/19
[16:13:29.382]     INFO: ROC 0 masking pixel 51/20
[16:13:29.382]     INFO: ROC 0 masking pixel 51/21
[16:13:29.382]     INFO: ROC 0 masking pixel 51/22
[16:13:29.382]     INFO: ROC 0 masking pixel 51/23
[16:13:29.382]     INFO: ROC 0 masking pixel 51/24
[16:13:29.382]     INFO: ROC 0 masking pixel 51/25
[16:13:29.382]     INFO: ROC 0 masking pixel 51/26
[16:13:29.382]     INFO: ROC 0 masking pixel 51/27
[16:13:29.382]     INFO: ROC 0 masking pixel 51/28
[16:13:29.382]     INFO: ROC 0 masking pixel 51/29
[16:13:29.382]     INFO: ROC 0 masking pixel 51/30
[16:13:29.382]     INFO: ROC 0 masking pixel 51/31
[16:13:29.382]     INFO: ROC 0 masking pixel 51/32
[16:13:29.382]     INFO: ROC 0 masking pixel 51/33
[16:13:29.382]     INFO: ROC 0 masking pixel 51/34
[16:13:29.382]     INFO: ROC 0 masking pixel 51/35
[16:13:29.382]     INFO: ROC 0 masking pixel 51/36
[16:13:29.382]     INFO: ROC 0 masking pixel 51/37
[16:13:29.382]     INFO: ROC 0 masking pixel 51/38
[16:13:29.382]     INFO: ROC 0 masking pixel 51/39
[16:13:29.382]     INFO: ROC 0 masking pixel 51/40
[16:13:29.382]     INFO: ROC 0 masking pixel 51/41
[16:13:29.382]     INFO: ROC 0 masking pixel 51/42
[16:13:29.382]     INFO: ROC 0 masking pixel 51/43
[16:13:29.382]     INFO: ROC 0 masking pixel 51/44
[16:13:29.382]     INFO: ROC 0 masking pixel 51/45
[16:13:29.382]     INFO: ROC 0 masking pixel 51/46
[16:13:29.383]     INFO: ROC 0 masking pixel 51/47
[16:13:29.383]     INFO: ROC 0 masking pixel 51/48
[16:13:29.383]     INFO: ROC 0 masking pixel 51/49
[16:13:29.383]     INFO: ROC 0 masking pixel 51/50
[16:13:29.383]     INFO: ROC 0 masking pixel 51/51
[16:13:29.383]     INFO: ROC 0 masking pixel 51/56
[16:13:29.383]     INFO: ROC 0 masking pixel 51/57
[16:13:29.383]     INFO: ROC 0 masking pixel 51/58
[16:13:29.383]     INFO: ROC 0 masking pixel 51/60
[16:13:29.383]     INFO: ROC 0 masking pixel 51/61
[16:13:29.383]     INFO: ROC 0 masking pixel 51/62
[16:13:29.383]     INFO: ROC 1 masking pixel 29/10
[16:13:29.383]     INFO: ROC 1 masking pixel 29/11
[16:13:29.383]     INFO: ROC 1 masking pixel 29/12
[16:13:29.383]     INFO: ROC 1 masking pixel 29/13
[16:13:29.383]     INFO: ROC 1 masking pixel 29/14
[16:13:29.383]     INFO: ROC 1 masking pixel 30/9
[16:13:29.383]     INFO: ROC 1 masking pixel 30/10
[16:13:29.383]     INFO: ROC 1 masking pixel 30/11
[16:13:29.383]     INFO: ROC 1 masking pixel 30/12
[16:13:29.383]     INFO: ROC 1 masking pixel 30/13
[16:13:29.383]     INFO: ROC 1 masking pixel 30/14
[16:13:29.383]     INFO: ROC 1 masking pixel 30/15
[16:13:29.383]     INFO: ROC 1 masking pixel 31/8
[16:13:29.383]     INFO: ROC 1 masking pixel 31/9
[16:13:29.383]     INFO: ROC 1 masking pixel 31/10
[16:13:29.383]     INFO: ROC 1 masking pixel 31/11
[16:13:29.383]     INFO: ROC 1 masking pixel 31/12
[16:13:29.383]     INFO: ROC 1 masking pixel 31/13
[16:13:29.383]     INFO: ROC 1 masking pixel 31/14
[16:13:29.383]     INFO: ROC 1 masking pixel 31/15
[16:13:29.383]     INFO: ROC 1 masking pixel 31/16
[16:13:29.383]     INFO: ROC 1 masking pixel 32/9
[16:13:29.383]     INFO: ROC 1 masking pixel 32/10
[16:13:29.383]     INFO: ROC 1 masking pixel 32/11
[16:13:29.383]     INFO: ROC 1 masking pixel 32/12
[16:13:29.383]     INFO: ROC 1 masking pixel 32/13
[16:13:29.383]     INFO: ROC 1 masking pixel 32/14
[16:13:29.383]     INFO: ROC 1 masking pixel 32/15
[16:13:29.383]     INFO: ROC 1 masking pixel 32/16
[16:13:29.383]     INFO: ROC 1 masking pixel 33/10
[16:13:29.383]     INFO: ROC 1 masking pixel 33/11
[16:13:29.383]     INFO: ROC 1 masking pixel 33/12
[16:13:29.383]     INFO: ROC 1 masking pixel 33/13
[16:13:29.383]     INFO: ROC 1 masking pixel 33/14
[16:13:29.383]     INFO: ROC 1 masking pixel 33/15
[16:13:29.383]     INFO: ROC 1 masking pixel 33/26
[16:13:29.383]     INFO: ROC 1 masking pixel 33/27
[16:13:29.383]     INFO: ROC 1 masking pixel 34/9
[16:13:29.384]     INFO: ROC 1 masking pixel 34/10
[16:13:29.384]     INFO: ROC 1 masking pixel 34/11
[16:13:29.384]     INFO: ROC 1 masking pixel 34/12
[16:13:29.384]     INFO: ROC 1 masking pixel 34/13
[16:13:29.384]     INFO: ROC 1 masking pixel 34/26
[16:13:29.384]     INFO: ROC 1 masking pixel 34/27
[16:13:29.384]     INFO: ROC 1 masking pixel 34/28
[16:13:29.384]     INFO: ROC 1 masking pixel 35/9
[16:13:29.384]     INFO: ROC 1 masking pixel 35/10
[16:13:29.384]     INFO: ROC 1 masking pixel 35/11
[16:13:29.384]     INFO: ROC 1 masking pixel 35/12
[16:13:29.384]     INFO: ROC 1 masking pixel 35/13
[16:13:29.384]     INFO: ROC 1 masking pixel 35/14
[16:13:29.384]     INFO: ROC 1 masking pixel 35/15
[16:13:29.384]     INFO: ROC 1 masking pixel 35/16
[16:13:29.384]     INFO: ROC 1 masking pixel 35/25
[16:13:29.384]     INFO: ROC 1 masking pixel 35/26
[16:13:29.384]     INFO: ROC 1 masking pixel 35/27
[16:13:29.384]     INFO: ROC 1 masking pixel 35/28
[16:13:29.384]     INFO: ROC 1 masking pixel 35/29
[16:13:29.384]     INFO: ROC 1 masking pixel 35/37
[16:13:29.384]     INFO: ROC 1 masking pixel 35/38
[16:13:29.384]     INFO: ROC 1 masking pixel 36/27
[16:13:29.384]     INFO: ROC 1 masking pixel 36/38
[16:13:29.384]     INFO: ROC 1 masking pixel 36/40
[16:13:29.384]     INFO: ROC 1 masking pixel 36/42
[16:13:29.384]     INFO: ROC 1 masking pixel 37/41
[16:13:29.384]     INFO: ROC 1 masking pixel 37/42
[16:13:29.384]     INFO: ROC 1 masking pixel 37/43
[16:13:29.384]     INFO: ROC 1 masking pixel 37/48
[16:13:29.384]     INFO: ROC 1 masking pixel 37/49
[16:13:29.384]     INFO: ROC 1 masking pixel 37/53
[16:13:29.384]     INFO: ROC 1 masking pixel 37/54
[16:13:29.384]     INFO: ROC 1 masking pixel 38/48
[16:13:29.384]     INFO: ROC 1 masking pixel 38/49
[16:13:29.384]     INFO: ROC 1 masking pixel 38/50
[16:13:29.384]     INFO: ROC 1 masking pixel 38/51
[16:13:29.384]     INFO: ROC 1 masking pixel 38/52
[16:13:29.384]     INFO: ROC 1 masking pixel 38/53
[16:13:29.384]     INFO: ROC 1 masking pixel 38/54
[16:13:29.384]     INFO: ROC 1 masking pixel 39/51
[16:13:29.384]     INFO: ROC 1 masking pixel 39/52
[16:13:29.384]     INFO: ROC 1 masking pixel 39/53
[16:13:29.384]     INFO: ROC 1 masking pixel 39/54
[16:13:29.384]     INFO: ROC 1 masking pixel 39/55
[16:13:29.384]     INFO: ROC 1 masking pixel 39/56
[16:13:29.384]     INFO: ROC 1 masking pixel 39/57
[16:13:29.384]     INFO: ROC 1 masking pixel 39/58
[16:13:29.385]     INFO: ROC 1 masking pixel 40/53
[16:13:29.385]     INFO: ROC 1 masking pixel 40/57
[16:13:29.385]     INFO: ROC 1 masking pixel 40/58
[16:13:29.385]     INFO: ROC 1 masking pixel 40/59
[16:13:29.387]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:30.182]     INFO: Expecting 41600 events.
[16:13:33.975]     INFO: 41600 events read in total (3266ms).
[16:13:33.980]     INFO: Test took 4593ms.
[16:13:34.125]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:34.125]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 801887
[16:13:34.125]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step0_C0 .. HR_xeff_CalDelScan_step0_C15
[16:13:34.126]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:34.184]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:34.850]     INFO: Expecting 41600 events.
[16:13:38.728]     INFO: 41600 events read in total (3351ms).
[16:13:38.733]     INFO: Test took 4549ms.
[16:13:38.868]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:38.868]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 809206
[16:13:38.868]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step1_C0 .. HR_xeff_CalDelScan_step1_C15
[16:13:38.869]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:38.930]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:39.598]     INFO: Expecting 41600 events.
[16:13:43.508]     INFO: 41600 events read in total (3383ms).
[16:13:43.513]     INFO: Test took 4583ms.
[16:13:43.654]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:43.654]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 811294
[16:13:43.654]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step2_C0 .. HR_xeff_CalDelScan_step2_C15
[16:13:43.655]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:43.717]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:44.383]     INFO: Expecting 41600 events.
[16:13:48.335]     INFO: 41600 events read in total (3426ms).
[16:13:48.341]     INFO: Test took 4624ms.
[16:13:48.488]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:48.488]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 811651
[16:13:48.488]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step3_C0 .. HR_xeff_CalDelScan_step3_C15
[16:13:48.488]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:48.554]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:49.224]     INFO: Expecting 41600 events.
[16:13:53.152]     INFO: 41600 events read in total (3402ms).
[16:13:53.157]     INFO: Test took 4603ms.
[16:13:53.292]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:53.292]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812077
[16:13:53.292]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step4_C0 .. HR_xeff_CalDelScan_step4_C15
[16:13:53.292]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:53.357]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:54.025]     INFO: Expecting 41600 events.
[16:13:57.952]     INFO: 41600 events read in total (3400ms).
[16:13:57.957]     INFO: Test took 4600ms.
[16:13:58.091]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:13:58.091]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812147
[16:13:58.091]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step5_C0 .. HR_xeff_CalDelScan_step5_C15
[16:13:58.091]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:13:58.157]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:13:58.824]     INFO: Expecting 41600 events.
[16:14:02.781]     INFO: 41600 events read in total (3430ms).
[16:14:02.787]     INFO: Test took 4630ms.
[16:14:02.926]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:02.926]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812656
[16:14:02.926]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step6_C0 .. HR_xeff_CalDelScan_step6_C15
[16:14:02.926]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:02.989]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:03.655]     INFO: Expecting 41600 events.
[16:14:07.589]     INFO: 41600 events read in total (3408ms).
[16:14:07.594]     INFO: Test took 4605ms.
[16:14:07.729]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:07.729]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 810040
[16:14:07.729]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step7_C0 .. HR_xeff_CalDelScan_step7_C15
[16:14:07.729]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:07.792]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:08.458]     INFO: Expecting 41600 events.
[16:14:12.407]     INFO: 41600 events read in total (3422ms).
[16:14:12.412]     INFO: Test took 4620ms.
[16:14:12.546]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:12.546]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 811658
[16:14:12.546]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step8_C0 .. HR_xeff_CalDelScan_step8_C15
[16:14:12.547]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:12.609]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:13.275]     INFO: Expecting 41600 events.
[16:14:17.210]     INFO: 41600 events read in total (3408ms).
[16:14:17.215]     INFO: Test took 4606ms.
[16:14:17.349]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:17.349]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 810817
[16:14:17.349]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step9_C0 .. HR_xeff_CalDelScan_step9_C15
[16:14:17.350]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:17.413]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:18.078]     INFO: Expecting 41600 events.
[16:14:22.017]     INFO: 41600 events read in total (3412ms).
[16:14:22.022]     INFO: Test took 4609ms.
[16:14:22.164]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:22.164]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 813792
[16:14:22.164]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step10_C0 .. HR_xeff_CalDelScan_step10_C15
[16:14:22.165]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:22.232]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:22.899]     INFO: Expecting 41600 events.
[16:14:26.840]     INFO: 41600 events read in total (3414ms).
[16:14:26.845]     INFO: Test took 4613ms.
[16:14:26.979]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:26.979]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812398
[16:14:26.979]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step11_C0 .. HR_xeff_CalDelScan_step11_C15
[16:14:26.980]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:27.043]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:27.708]     INFO: Expecting 41600 events.
[16:14:31.633]     INFO: 41600 events read in total (3398ms).
[16:14:31.638]     INFO: Test took 4595ms.
[16:14:31.807]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:31.807]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 813330
[16:14:31.807]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step12_C0 .. HR_xeff_CalDelScan_step12_C15
[16:14:31.807]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:31.869]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:32.535]     INFO: Expecting 41600 events.
[16:14:36.467]     INFO: 41600 events read in total (3405ms).
[16:14:36.472]     INFO: Test took 4603ms.
[16:14:36.607]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:36.607]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 810990
[16:14:36.607]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step13_C0 .. HR_xeff_CalDelScan_step13_C15
[16:14:36.608]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:36.670]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:37.335]     INFO: Expecting 41600 events.
[16:14:41.273]     INFO: 41600 events read in total (3411ms).
[16:14:41.278]     INFO: Test took 4608ms.
[16:14:41.411]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:41.411]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812610
[16:14:41.411]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step14_C0 .. HR_xeff_CalDelScan_step14_C15
[16:14:41.412]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:41.475]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:42.140]     INFO: Expecting 41600 events.
[16:14:46.088]     INFO: 41600 events read in total (3421ms).
[16:14:46.093]     INFO: Test took 4618ms.
[16:14:46.227]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:46.227]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 812003
[16:14:46.227]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step15_C0 .. HR_xeff_CalDelScan_step15_C15
[16:14:46.228]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:46.293]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:46.960]     INFO: Expecting 41600 events.
[16:14:50.909]     INFO: 41600 events read in total (3422ms).
[16:14:50.914]     INFO: Test took 4621ms.
[16:14:51.079]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:51.079]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 810721
[16:14:51.079]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step16_C0 .. HR_xeff_CalDelScan_step16_C15
[16:14:51.079]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:51.143]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:51.810]     INFO: Expecting 41600 events.
[16:14:55.761]     INFO: 41600 events read in total (3424ms).
[16:14:55.766]     INFO: Test took 4623ms.
[16:14:55.899]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:14:55.899]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 811142
[16:14:55.899]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step17_C0 .. HR_xeff_CalDelScan_step17_C15
[16:14:55.900]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:14:55.963]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:14:56.629]     INFO: Expecting 41600 events.
[16:15:00.529]     INFO: 41600 events read in total (3374ms).
[16:15:00.535]     INFO: Test took 4572ms.
[16:15:00.668]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:15:00.668]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 809692
[16:15:00.668]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step18_C0 .. HR_xeff_CalDelScan_step18_C15
[16:15:00.669]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:15:00.731]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:15:01.400]     INFO: Expecting 41600 events.
[16:15:05.161]     INFO: 41600 events read in total (3234ms).
[16:15:05.166]     INFO: Test took 4435ms.
[16:15:05.300]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:15:05.300]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 803241
[16:15:05.300]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists HR_xeff_CalDelScan_step19_C0 .. HR_xeff_CalDelScan_step19_C15
[16:15:05.301]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:15:05.583]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  0: caldel = 154 eff = 0.983534
[16:15:05.584]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  1: caldel = 161 eff = 0.978341
[16:15:05.584]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  2: caldel = 171 eff = 0.998101
[16:15:05.584]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  3: caldel = 170 eff = 0.99762
[16:15:05.584]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  4: caldel = 161 eff = 0.996635
[16:15:05.585]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  5: caldel = 146 eff = 0.996659
[16:15:05.585]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  6: caldel = 173 eff = 0.99637
[16:15:05.585]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  7: caldel = 180 eff = 0.996563
[16:15:05.585]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  8: caldel = 190 eff = 0.99625
[16:15:05.585]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc  9: caldel = 138 eff = 0.996202
[16:15:05.586]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 10: caldel = 166 eff = 0.996322
[16:15:05.586]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 11: caldel = 141 eff = 0.996226
[16:15:05.586]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 12: caldel = 151 eff = 0.996274
[16:15:05.586]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 13: caldel = 141 eff = 0.996563
[16:15:05.587]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 14: caldel = 125 eff = 0.999159
[16:15:05.587]    DEBUG: <PixTestHighRate.cc/doCalDelScan:L435> roc 15: caldel = 138 eff = 0.999159
[16:15:33.450]    DEBUG: <PixTab.cc/buttonClicked:L308> xxxPressed():  xpixelalive
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/runCommand:L165> running command: xpixelalive
[16:15:33.450]     INFO:    ----------------------------------------------------------------------
[16:15:33.450]     INFO:    PixTestHighRate::xPixelAlive() ntrig = 50, vcal = 200
[16:15:33.450]     INFO:    ----------------------------------------------------------------------
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: clk: 4
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: ctr: 4
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: sda: 19
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: tin: 9
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: level: 15
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L464>  old set: triggerdelay: 0
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: clk: 4
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: ctr: 4
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: sda: 19
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: tin: 9
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: level: 15
[16:15:33.450]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L480>  setting: triggerdelay: 20
[16:15:33.467]     INFO: ROC 0 masking pixel 50/5
[16:15:33.467]     INFO: ROC 0 masking pixel 50/6
[16:15:33.467]     INFO: ROC 0 masking pixel 50/7
[16:15:33.467]     INFO: ROC 0 masking pixel 50/8
[16:15:33.467]     INFO: ROC 0 masking pixel 50/9
[16:15:33.467]     INFO: ROC 0 masking pixel 50/10
[16:15:33.467]     INFO: ROC 0 masking pixel 50/11
[16:15:33.467]     INFO: ROC 0 masking pixel 50/12
[16:15:33.467]     INFO: ROC 0 masking pixel 50/13
[16:15:33.467]     INFO: ROC 0 masking pixel 50/15
[16:15:33.467]     INFO: ROC 0 masking pixel 51/3
[16:15:33.467]     INFO: ROC 0 masking pixel 51/4
[16:15:33.467]     INFO: ROC 0 masking pixel 51/5
[16:15:33.467]     INFO: ROC 0 masking pixel 51/6
[16:15:33.467]     INFO: ROC 0 masking pixel 51/7
[16:15:33.467]     INFO: ROC 0 masking pixel 51/8
[16:15:33.467]     INFO: ROC 0 masking pixel 51/9
[16:15:33.467]     INFO: ROC 0 masking pixel 51/10
[16:15:33.467]     INFO: ROC 0 masking pixel 51/11
[16:15:33.467]     INFO: ROC 0 masking pixel 51/12
[16:15:33.468]     INFO: ROC 0 masking pixel 51/13
[16:15:33.468]     INFO: ROC 0 masking pixel 51/14
[16:15:33.468]     INFO: ROC 0 masking pixel 51/15
[16:15:33.468]     INFO: ROC 0 masking pixel 51/16
[16:15:33.468]     INFO: ROC 0 masking pixel 51/17
[16:15:33.468]     INFO: ROC 0 masking pixel 51/18
[16:15:33.468]     INFO: ROC 0 masking pixel 51/19
[16:15:33.468]     INFO: ROC 0 masking pixel 51/20
[16:15:33.468]     INFO: ROC 0 masking pixel 51/21
[16:15:33.468]     INFO: ROC 0 masking pixel 51/22
[16:15:33.468]     INFO: ROC 0 masking pixel 51/23
[16:15:33.468]     INFO: ROC 0 masking pixel 51/24
[16:15:33.468]     INFO: ROC 0 masking pixel 51/25
[16:15:33.468]     INFO: ROC 0 masking pixel 51/26
[16:15:33.468]     INFO: ROC 0 masking pixel 51/27
[16:15:33.468]     INFO: ROC 0 masking pixel 51/28
[16:15:33.468]     INFO: ROC 0 masking pixel 51/29
[16:15:33.468]     INFO: ROC 0 masking pixel 51/30
[16:15:33.468]     INFO: ROC 0 masking pixel 51/31
[16:15:33.468]     INFO: ROC 0 masking pixel 51/32
[16:15:33.468]     INFO: ROC 0 masking pixel 51/33
[16:15:33.468]     INFO: ROC 0 masking pixel 51/34
[16:15:33.468]     INFO: ROC 0 masking pixel 51/35
[16:15:33.468]     INFO: ROC 0 masking pixel 51/36
[16:15:33.468]     INFO: ROC 0 masking pixel 51/37
[16:15:33.468]     INFO: ROC 0 masking pixel 51/38
[16:15:33.468]     INFO: ROC 0 masking pixel 51/39
[16:15:33.468]     INFO: ROC 0 masking pixel 51/40
[16:15:33.468]     INFO: ROC 0 masking pixel 51/41
[16:15:33.468]     INFO: ROC 0 masking pixel 51/42
[16:15:33.468]     INFO: ROC 0 masking pixel 51/43
[16:15:33.468]     INFO: ROC 0 masking pixel 51/44
[16:15:33.468]     INFO: ROC 0 masking pixel 51/45
[16:15:33.468]     INFO: ROC 0 masking pixel 51/46
[16:15:33.468]     INFO: ROC 0 masking pixel 51/47
[16:15:33.468]     INFO: ROC 0 masking pixel 51/48
[16:15:33.468]     INFO: ROC 0 masking pixel 51/49
[16:15:33.468]     INFO: ROC 0 masking pixel 51/50
[16:15:33.468]     INFO: ROC 0 masking pixel 51/51
[16:15:33.468]     INFO: ROC 0 masking pixel 51/56
[16:15:33.468]     INFO: ROC 0 masking pixel 51/57
[16:15:33.468]     INFO: ROC 0 masking pixel 51/58
[16:15:33.468]     INFO: ROC 0 masking pixel 51/60
[16:15:33.468]     INFO: ROC 0 masking pixel 51/61
[16:15:33.469]     INFO: ROC 0 masking pixel 51/62
[16:15:33.469]     INFO: ROC 1 masking pixel 29/10
[16:15:33.469]     INFO: ROC 1 masking pixel 29/11
[16:15:33.469]     INFO: ROC 1 masking pixel 29/12
[16:15:33.469]     INFO: ROC 1 masking pixel 29/13
[16:15:33.469]     INFO: ROC 1 masking pixel 29/14
[16:15:33.469]     INFO: ROC 1 masking pixel 30/9
[16:15:33.469]     INFO: ROC 1 masking pixel 30/10
[16:15:33.469]     INFO: ROC 1 masking pixel 30/11
[16:15:33.469]     INFO: ROC 1 masking pixel 30/12
[16:15:33.469]     INFO: ROC 1 masking pixel 30/13
[16:15:33.469]     INFO: ROC 1 masking pixel 30/14
[16:15:33.469]     INFO: ROC 1 masking pixel 30/15
[16:15:33.469]     INFO: ROC 1 masking pixel 31/8
[16:15:33.469]     INFO: ROC 1 masking pixel 31/9
[16:15:33.469]     INFO: ROC 1 masking pixel 31/10
[16:15:33.469]     INFO: ROC 1 masking pixel 31/11
[16:15:33.469]     INFO: ROC 1 masking pixel 31/12
[16:15:33.469]     INFO: ROC 1 masking pixel 31/13
[16:15:33.469]     INFO: ROC 1 masking pixel 31/14
[16:15:33.469]     INFO: ROC 1 masking pixel 31/15
[16:15:33.469]     INFO: ROC 1 masking pixel 31/16
[16:15:33.469]     INFO: ROC 1 masking pixel 32/9
[16:15:33.469]     INFO: ROC 1 masking pixel 32/10
[16:15:33.469]     INFO: ROC 1 masking pixel 32/11
[16:15:33.469]     INFO: ROC 1 masking pixel 32/12
[16:15:33.469]     INFO: ROC 1 masking pixel 32/13
[16:15:33.469]     INFO: ROC 1 masking pixel 32/14
[16:15:33.469]     INFO: ROC 1 masking pixel 32/15
[16:15:33.469]     INFO: ROC 1 masking pixel 32/16
[16:15:33.469]     INFO: ROC 1 masking pixel 33/10
[16:15:33.469]     INFO: ROC 1 masking pixel 33/11
[16:15:33.469]     INFO: ROC 1 masking pixel 33/12
[16:15:33.469]     INFO: ROC 1 masking pixel 33/13
[16:15:33.469]     INFO: ROC 1 masking pixel 33/14
[16:15:33.469]     INFO: ROC 1 masking pixel 33/15
[16:15:33.469]     INFO: ROC 1 masking pixel 33/26
[16:15:33.469]     INFO: ROC 1 masking pixel 33/27
[16:15:33.469]     INFO: ROC 1 masking pixel 34/9
[16:15:33.469]     INFO: ROC 1 masking pixel 34/10
[16:15:33.469]     INFO: ROC 1 masking pixel 34/11
[16:15:33.469]     INFO: ROC 1 masking pixel 34/12
[16:15:33.469]     INFO: ROC 1 masking pixel 34/13
[16:15:33.469]     INFO: ROC 1 masking pixel 34/26
[16:15:33.469]     INFO: ROC 1 masking pixel 34/27
[16:15:33.469]     INFO: ROC 1 masking pixel 34/28
[16:15:33.469]     INFO: ROC 1 masking pixel 35/9
[16:15:33.469]     INFO: ROC 1 masking pixel 35/10
[16:15:33.469]     INFO: ROC 1 masking pixel 35/11
[16:15:33.469]     INFO: ROC 1 masking pixel 35/12
[16:15:33.470]     INFO: ROC 1 masking pixel 35/13
[16:15:33.470]     INFO: ROC 1 masking pixel 35/14
[16:15:33.470]     INFO: ROC 1 masking pixel 35/15
[16:15:33.470]     INFO: ROC 1 masking pixel 35/16
[16:15:33.470]     INFO: ROC 1 masking pixel 35/25
[16:15:33.470]     INFO: ROC 1 masking pixel 35/26
[16:15:33.470]     INFO: ROC 1 masking pixel 35/27
[16:15:33.470]     INFO: ROC 1 masking pixel 35/28
[16:15:33.470]     INFO: ROC 1 masking pixel 35/29
[16:15:33.470]     INFO: ROC 1 masking pixel 35/37
[16:15:33.470]     INFO: ROC 1 masking pixel 35/38
[16:15:33.470]     INFO: ROC 1 masking pixel 36/27
[16:15:33.470]     INFO: ROC 1 masking pixel 36/38
[16:15:33.470]     INFO: ROC 1 masking pixel 36/40
[16:15:33.470]     INFO: ROC 1 masking pixel 36/42
[16:15:33.470]     INFO: ROC 1 masking pixel 37/41
[16:15:33.470]     INFO: ROC 1 masking pixel 37/42
[16:15:33.470]     INFO: ROC 1 masking pixel 37/43
[16:15:33.470]     INFO: ROC 1 masking pixel 37/48
[16:15:33.470]     INFO: ROC 1 masking pixel 37/49
[16:15:33.470]     INFO: ROC 1 masking pixel 37/53
[16:15:33.470]     INFO: ROC 1 masking pixel 37/54
[16:15:33.470]     INFO: ROC 1 masking pixel 38/48
[16:15:33.470]     INFO: ROC 1 masking pixel 38/49
[16:15:33.470]     INFO: ROC 1 masking pixel 38/50
[16:15:33.470]     INFO: ROC 1 masking pixel 38/51
[16:15:33.470]     INFO: ROC 1 masking pixel 38/52
[16:15:33.470]     INFO: ROC 1 masking pixel 38/53
[16:15:33.470]     INFO: ROC 1 masking pixel 38/54
[16:15:33.470]     INFO: ROC 1 masking pixel 39/51
[16:15:33.470]     INFO: ROC 1 masking pixel 39/52
[16:15:33.470]     INFO: ROC 1 masking pixel 39/53
[16:15:33.470]     INFO: ROC 1 masking pixel 39/54
[16:15:33.470]     INFO: ROC 1 masking pixel 39/55
[16:15:33.470]     INFO: ROC 1 masking pixel 39/56
[16:15:33.470]     INFO: ROC 1 masking pixel 39/57
[16:15:33.470]     INFO: ROC 1 masking pixel 39/58
[16:15:33.470]     INFO: ROC 1 masking pixel 40/53
[16:15:33.470]     INFO: ROC 1 masking pixel 40/57
[16:15:33.470]     INFO: ROC 1 masking pixel 40/58
[16:15:33.470]     INFO: ROC 1 masking pixel 40/59
[16:15:33.471]    DEBUG: <PixTest.cc/efficiencyMaps:L396>       attempt #0
[16:15:34.139]     INFO: Expecting 208000 events.
[16:15:50.423]     INFO: 208000 events read in total (15757ms).
[16:15:50.442]     INFO: Test took 16971ms.
[16:15:51.271]     INFO: Fetched DAQ statistics. Counters are being reset now.
[16:15:51.271]    DEBUG: <PixTest.cc/efficiencyMaps:L407>  eff result size = 3749100
[16:15:51.271]    DEBUG: <PixTest.cc/efficiencyMaps:L412> Create hists highRate_C0 .. highRate_C15
[16:15:51.272]    DEBUG: <PixTest.cc/efficiencyMaps:L426> booking xray maps for unmasked detector
[16:15:51.767]     INFO: number of dead pixels (per ROC):    65   90    0    0    0    0    0    0    0    0    0    0    0    0    0    0
[16:15:51.767]     INFO: number of red-efficiency pixels:   252  106  399  613  689  676  668  679  755  722  666  729  661  397  194  233
[16:15:51.767]     INFO: number of X-ray hits detected:    125816 17874 185318 275489 291583 288371 302205 282216 309922 305063 298597 282922 284750 180711 117852 134006
[16:15:51.767]     INFO: number of triggers sent (total per ROC):  208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000 208000
[16:15:51.768]     INFO: number of Vcal hits detected:  204556 203482 207543 207284 207231 207215 207251 207215 207130 207170 207231 207178 207244 207555 207796 207753
[16:15:51.768]     INFO: Vcal hit fiducial efficiency (%):  99.9 100.0 99.8 99.7 99.7 99.7 99.7 99.6 99.6 99.6 99.7 99.6 99.7 99.8 99.9 99.9
[16:15:51.768]     INFO: Vcal hit overall efficiency (%):  98.3 97.8 99.8 99.7 99.6 99.6 99.6 99.6 99.6 99.6 99.6 99.6 99.6 99.8 99.9 99.9
[16:15:51.768]     INFO: X-ray hit rate [MHz/cm2]:  36.9 5.2 54.3 80.7 85.5 84.5 88.6 82.7 90.8 89.4 87.5 82.9 83.5 53.0 34.5 39.3
[16:15:51.768]     INFO: PixTestHighRate::doXPixelAlive() done
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: clk: 4
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: ctr: 4
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: sda: 19
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: tin: 9
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: level: 15
[16:15:51.819]    DEBUG: <PixTestHighRate.cc/doXPixelAlive:L599>  resetting: triggerdelay: 0
[16:15:51.819]     INFO: PixTest::       pg_setup set to default.
[16:16:36.346]    DEBUG: <PixTest.cc/moduleMap:L1029> moduleMap histname: what
[16:16:36.346]    DEBUG: <PixTest.cc/moduleMap:L1039> h1->GetName() = highRate_xraymap_C11_V0 -> highRate_xraymap_mod
[16:16:40.082]    DEBUG: <PixGui.cc/handleButtons:L396> PixGui::exit called
[16:16:40.082]    DEBUG: <PixGui.cc/CloseWindow:L335> Final Analog Current: 398.7mA
[16:16:40.083]    DEBUG: <PixGui.cc/CloseWindow:L336> Final Digital Current: 471.1mA
[16:16:40.083]    DEBUG: <PixGui.cc/CloseWindow:L337> Final Module Temperature: -0.2 C
[16:16:40.083]    DEBUG: <PixTestBBMap.cc/~PixTestBBMap:L97> PixTestBBMap dtor
[16:16:40.083]    DEBUG: <PixTestBB2Map.cc/~PixTestBB2Map:L115> PixTestBB2Map dtor
[16:16:40.083]    DEBUG: <PixTestBB3Map.cc/~PixTestBB3Map:L99> PixTestBB3Map dtor
[16:16:40.084]    DEBUG: <PixTestBB4Map.cc/~PixTestBB4Map:L118> PixTestBB4Map dtor
[16:16:40.084]    DEBUG: <PixTestCmd.cc/~PixTestCmd:L78> PixTestCmd dtor
[16:16:40.084]    DEBUG: <PixTestDaq.cc/~PixTestDaq:L37> PixTestDaq dtor
[16:16:40.084]    DEBUG: <PixTestDacDacScan.cc/~PixTestDacDacScan:L136> PixTestDacDacScan dtor
[16:16:40.084]    DEBUG: <PixTestDacScan.cc/~PixTestDacScan:L129> PixTestDacScan dtor
[16:16:40.084]    DEBUG: <PixTestGainPedestal.cc/~PixTestGainPedestal:L125> PixTestGainPedestal dtor
[16:16:40.084]    DEBUG: <PixTestHighRate.cc/~PixTestHighRate:L258> PixTestHighRate dtor
[16:16:40.177]    DEBUG: <PixTestIV.cc/~PixTestIV:L96> PixTestIV dtor
[16:16:40.177]    DEBUG: <PixTestAlive.cc/~PixTestAlive:L115> PixTestAlive dtor
[16:16:40.186]    DEBUG: <PixTestPretest.cc/~PixTestPretest:L136> PixTestPretest dtor
[16:16:40.186]    DEBUG: <PixTestReadback.cc/~PixTestReadback:L89> PixTestReadback dtor, saving tree ... 
[16:16:40.187]    DEBUG: <PixTestScurves.cc/~PixTestScurves:L142> PixTestScurves dtor
[16:16:40.187]    DEBUG: <PixTestTiming.cc/~PixTestTiming:L96> PixTestTiming dtor
[16:16:40.187]    DEBUG: <PixTestTrim.cc/~PixTestTrim:L103> PixTestTrim dtor
[16:16:40.187]    DEBUG: <PixTestXray.cc/~PixTestXray:L218> PixTestXray dtor
[16:16:40.189]    QUIET: Connection to board 58 closed.
[16:16:40.269]    DEBUG: <PixMonitor.cc/dumpSummaries:L39> PixMonitor::dumpSummaries