| A ripple counter has many intermediate states that are cycled through before the expected value stabalizes on the output. This is because the state changes in the later stages occur in response to state changes in earlier stages and it takes a finite amount of time for all these changes to propagate through the logic. A synchronous counter determines the next state of the outputs in advance of an input clock signal, so all outputs change simultaneously to this new value. |
| Clock signals often have to drive many loads and therefore need lower impedance driver circuits and low latency signal routing. Normal logic signals usually don't drive as many loads and don't necessarily require very low latency, so long as their values stabalize before clock signals that sample them arrive at latch or similar logic. |