Department of Physics
Condensed Matter Seminar

My presentation will be divided in two main sections. In the first part of my talk I will explain the advantages of graphene for electronic applications from a device physicist's prospective. I will present a simple argument why graphene nanostructures exhibit an intrinsic advantage when considering the gate delay in three-terminal device structures and explain why the possibility to operate in the quantum capacitance Cq limit provides additional benefits. In particular, I will emphasize the unique opportunity graphene offers for new types of devices and the distinct scaling advantages of graphene transistors in terms of reduced power consumption. The second part of my talk will focus on three experimental modules. I will discuss recent experimental results on the energy dependence of Cq that support the above statements and show initial evidence that scaling of the off-state in graphene transistors follows percolation theory rather than conventional diffusive transport equations. Last, I will present data on substantial contact resistance that seems to be universally present in case of metal contacted graphene transistors.