December 8, 1999

Revised: December16,1999

Dear Committee,

We are submitting the Si3 plan for assembly, testing and installation to you in revised form today. In September, after the delivery of the 1^st clamshell to Ithaca, the Si3 group reviewed the fabrication schedule for the remainder of the project. We estimated that the 2^nd clamshell would be completed and tested at Purdue and flown to Ithaca on November 1st. We met this date. We estimated that layer 3 would be completed and tested at Purdue by the end of October, again we met this date. Finally we estimated that layer 4 would be completed, to the extent that it was possible to do so, and the layer 3&4 assembly flown to Ithaca by December 2. This date was also met. The current status of the detector is that layers 1,2,3 are complete, layer 1 and 2 are mounted on the beam-pipe. Layer 3 has been tested and found to be in good working order. .Layer 4 misses three of 26 silicon ladders. These parts are in process and will be mounted in Ithaca.

Our ability to predict and meet the delivery dates was in large part due to the fact that, at this stage in the fabrication and assembly, each step in the process was well understood, and the range of problems that could occur, and the cures for problems, had largely been worked-out.

On Nov 13 a Si3 group meeting was held at Purdue that was devoted, in large part, to discussing and developing a schedule for Si3 assembly, installation and commissioning. The next day we re-convened and worked out in detail a week by week schedule. Subsequently further detail was added to that schedule and sent to Si3 for comments. The schedule has been updated to include the comments so far. The document was originally written as an internal Si3 document. Some effort has been invested to make the document intelligible to non-Si3 members. However there has been in-sufficient time to do this properly. The committee is encouraged to request clarification on all points that are unclear. A source of information with much greater detail is the Si3 group web-pages., for example http://www.physics.purdue.edu/cleosi3 and links therein.

The schedule concludes that a shutdown of CESR on Jan 30, with installation of Si3 commencing on Feb 8 is possible. This is a success-oriented schedule.

Note added Dec 16:

Layer 3/4 has now been installed around Layer 1/2 and the transition cones added.. After layer 3/4 was installed , all 18 ladders of layer 3 were tested at one end and are found to be in good health.

Testing is ongoing. Layer 4 cabling will begin soon. Missing layer 4 ladder status: one layer 4 ladder has now been completed, a second ladder is expected to be completed next week. The third ladder has been complete for sometime, it has an electrical problem but can be used as is if necessary. A spare layer 4 ladder is in process.

As a result of the productive meetings between the Si3 Review Committee and the Si3 group on December 10 and December 11 we are submitting a revised plan today. Changes to the original document are preceded by the text:"Note added Dec 16:" or similar.

. .

Ian Shipsey

(For the Si3 Group)

This document is organized as follows: a very brief overview of the detector is followed by more detailed descriptions of ongoing critical work on the DAQ, power supplies and slow control. This is then followed by the overall assembly and testing schedule showing activity week by week

This schedule, like all schedules, is a best guess. Although specific dates are shown below, the

fidelity of any schedule is commensurate with the available information. For the same reasons that we were able to accurately predict the dates for the arrival of the silicon in Ithaca, we can now predict with increased certainty the expected duration of the assembly on the beam pipe, the detector bench-marking and completion of the DAQ, power supply and slow control deliverables. Nevertheless, we are always vulnerable to unforeseen problems.

The plan presented here covers most of the remaining tasks needed to get Si3 ready for installation.

Additional details of the assembly on the beam-pipe and work required before installation are also provided. This detail is intended to convey the complex nature of these tasks and to enable all to better understand the assembly schedule and the constraints it imposes.

Very briefly; the Si3 detector is a four layer long barrel silicon strip tracking detector with expected performance of 17<S/N<60. It contains 447 double-sided wafers DC coupled with R/C off detector. All wafers in all layers are identical. The 447 wafers form 61 chains, called ladders, which vary in length from 15 cm (3 wafers) in layer 1 which is 2.5 cm from the IP , to 53 cm (10 wafers) in layer 4 which is 10 cm from the IP. Each ladder is readout at both ends by a double-side BeO hybrid which is connected to the silicon via a flexible Kapton circuit. The readout chain consists of a 128 channel R/C chip which connects each detector channel to the high voltage bus via a 60 Mohm bias resistor, and to the readout electronics via a 140 pF capacitor. The middle chip in the readout chain is the FEMME pre-amp and shaper. This is a multistage 128 channel chip, a front end charge sensitive pre-amplifier with noise performance of 5e/pF + 150e at 2 microsecond shaping time,

followed by a shaper stage. The combined gain of the two stages is 200 mV/MIP, with 5% linearity up to 5 MIPS. The last chip in the readout chain is the SVX_CLEO digitizer/sparsifier. This 128 channel chip is based on the FNAL/LBL_SVXII(b). Each channel on the chip has a comparator and an 8 bit Wilkinson ADC. The digitized results are stored in a FIFO. After digitiztation, sparsification is possible via a chip-wide threshold. Nearest neighbor logic, both within and across chips, allows for improved charge collection efficiency. To allow for common mode noise subtraction of the data one channel is always readout. A MIP produces 20,000 electron-hole pairs as it traverses 300 microns of silicon. Typical noise for layer 1 is about 350 e and for layer 4 it is about 750 e. S/N is excellent.

There are about 450,000 micro-strips in Si3 readout by 125,000 channels of electronics.

This should be compared to SVX which has 96 silicon wafers and 26,000 channels of readout electronics. Si3 is 5 times larger that SVX and is similar in size to the DELPHI detector.

The silicon ladders are supported at each end by a system of inter-connected cones, one cone for layers 1&2, a second cone for layers 3&4. At each end, the layer 1&2 cone and the layer 3&4 cone are connected to each other by a carbon fiber transition cone. In addition the layer 3&4 cones at each end are connected via a carbon fiber torsional cylinder radially located between layers 3 and 4. The layer 1&2 cones are in two halves that we call clamshells. During assembly at Purdue the two halves are separate structures which are subsequently "clam-shelled "around the beam-pipe at Cornell. This has just been completed. Layer 3&4 is also an independent structure during assembly at Purdue, which will be installed around the Layer 1&2 assembly beginning as early as next week.

During each ladder fabrication step at Purdue, and after assembly of each ladder on the cones, parts are electrically tested to determine the status of each channel (pedestal at full bias). These tests and others are being repeated and extended at Cornell by Eckhard and Jik upon receipt of the sub-assemblies, during assembly around the beam-pipe and finally as a multi-ladder system test.

Due to time limitations this document will not describe the earlier work done at Albany, Cornell, Kansas, Harvard, Ohio-State, Oklahoma and Purdue that enabled silicon detectors, flex circuits and hybrids to be designed, built and tested prior to arrival at Purdue. Nor will we describe the detailed fabrication steps at Purdue and elsewhere that have resulted in a complete Si3 detector. However, the Si3 detector, has been described extensively in the literature (at least 7 N.I.M. articles). Most of these articles, including figures, together with the talk transparencies can be found at http://www.physics.purdue.edu/cleosi3/talks.html

The most recent photographs of the detector are at http://www.physics.purdue.edu/cleosi3

And at http://www.lns.cornell.edu/restricted/figures/pix/Cleoiii/SI/FinalAssembly/index.htm

A. Overview:

The CLEO3 Silicon Detector (Si3) has 61 ladders which terminate in 122 readout hybrids. This is a summary of the electronics and associated software that are used to control and readout the hybrids. The hybrids are connected via Hybrid Cable pairs (one data and one power) to the backplane of the Crescent Crates. The eight Crescent Crates (four at each end of the detector) hold one Port Card for each hybrid. Each Crescent Crate also contains one Slow Control Buffer

Card, and in some cases a Temperature/Humidity Monitor Card (also known as the Gaidarev Card). The Port Cards are connected to the outside world via Port Card Cable pairs (one data and one power). The Port Card Data Cables go to the VME based Databoards which each service four Port Cards. Likewise the Port Card Power Cables go the VME based Power Distribution Boards. The Slow Control and Power Supply systems are discussed in other sections of this document.

The Si3 data stream is controlled and readout by the Data-boards. The VME side of these boards is essentially identical to the RICH Databoards. The detector side of the boards consists of four sequencer channels, each of which contains a gate array chip to control the hybrid and a fifo to hold the readout data. In between the fifos and the VME section there is a digital signal processor

(DSP), which extracts the data from the fifos, tags it with DAQ channel ID's, and makes it available for block transfers to the crate CPU and the DAQ datastream. The DSP is also available for data

manipulation such as a second stage of sparsification after common mode noise subtraction if we find it to be necessary (the SVX_cleo chips on the hybrid provide the first level).

The Port Cards provide the interface between the hybrids and three systems: readout (Databoards), power (Power Distribution Boards), and slow control (Kansas Boards via the Buffer Cards). For the datastream the Port Card serves primarily as a repeater taking the LVDS signals

and clocks from the Databoard and converting them to TTL signals and a PECL clock for the hybrid. The Port Card receives power from the Power Distribution boards and generates the necessary power and bias levels for the hybrid. It has 8 DACs and 16 ADCs which are used by

the Slow Control system to control and monitor these levels.

Finally the Crescent Crates provide an interface between the Port Cards and the Hybrid Cables. The backplane also connects the Port Cards to the Slow Control buffer card via a serial bus and address

lines.

B. Status of Components:

1. Crescent Crates: All eight have been delivered and tested. There are two partial backplanes available for ongoing testing at Harvard and Cornell. They were originally assembled with slightly magnetic screws, which are now being replaced with non-magnetic ones. (Alexey Ershov, Steve Sansone, Jeff Cherwinka)

2. Port Cards: 140 have been built, 130 of these tested OK and are delivered, (122 are needed). The failures will be recycled as spares. (Alexey Ershov, Sarah Harder, John Oliver)

3. Databoards: 45 boards were made and 35 were stuffed. Of these 9 have been programmed and tested, 7 more are waiting to be programmed, and 1 needs repair. We need a minimum of 32, but will probably install 34 in the detector leaving 14 open ports. (This allows each Databoard to have only one L1/2 hybrid attached and also means we have hot spares.) The remainder of the 35 stuffed boards will be ready by Jan 15, and we can have an additional five spares ready by Feb 15. (Daniel Kim, Charlie Strohman, John Oliver, GWB)

4. Hybrid Cables: The necessary 122 cable pairs have been fabricated and tested. Since there are different configurations for each layer we will make spares as needed during the detector assembly process (there are spare parts for about 15 data cables and about 8 power cables). These will be completed by Jan 15. (Jack O'Kane, GWB)

5. Port Card Cables: 140 pairs have been made and tested - 122 are needed. (Wilson EShop)

1. LabView test stand (SVXDAQ): This software has been in use several years and is currently used at Wilson for ladder testing and at Newman for hybrid repair/testing. The version in Wilson is capable of reading out an entire VME crate of Databoards (one half of the detector) and writing the data to a file for offline analysis. (GWB)

2. Load_Constants: This routine runs in the Databoard crate CPU and initializes both the databoard and hybrids and readies them for data taking. Eventually it will be initiated by the DAQ Begin Run function and will extract the necessary parameters from the database. A standalone version with constant parameters has been written and successfully tested. This version can be executed from a VXworks prompt and used for ladder testing, especially the single ladder currently installed in the detector. Integrating this routine into the DAQ should be completed by Jan 15. (GWB, Daniel Kim)

3. Standalone data logging: A temporary set of routines exist which run in the crate CPU and mimic SVXDAQ. A Databoard/hybrid combination can be run through a set of readout cycles with the data extracted from the databoard and written to a file. These routines can be used in conjunction with the standalone version of Load_Constants for ladder testing. (GWB, Daniel Kim)

4. DSP code: In order for the Databoard to make tagged data available for block transfers to the crate CPU and the DAQ datastream, it is necessary to program the DSP. A preliminary version of this code has been written and successfully tested. This version has a single input

buffer and the tagging is done with a fixed hybrid number. Efforts are now underway to integrate this into the DAQ (where the block transfers are essentially identical in format to those from RICH

databoards). The next version of this code will have circular input buffering and a variable tagging system which is keyed off the hybrid number (there are four different classes of hybrids each with a

different channel ordering scheme). The second version will be completed by Jan 1 and the DAQ integration should be complete by Jan 15. Future versions of the DSP code could include a second level of sparsification after common mode noise subtraction if this is required. (Daniel Kim, Eliott Lipeles)

All readout electronics components (plus spares) and software are currently ready and tested with the exception of:

1. Eight additional Databoards will be tested and in service by Jan 1 bringing the total to 17 (1/2 of the total needed). The next 18 will be ready Jan 15. Five spares should be ready by Feb 15.

2. The spare Hybrid Cable pairs will be fabricated and tested by Jan 15.

3. The Load_Constants routine should be integrated into the DAQ by Jan 15.

4. Version 2 of the DSP code with circular buffering and variable tagging will be ready by Jan 1. Integration of the DAQ should be complete by Jan 15.

We have:

All KU Boards to control port cards are in hand and tested.

All cables for KU board to Port card connection are in hand and tested.

KU crate installed in pit - no more needed.

Si detector Cooling is going to be monitored by the Central CLEO slow control system.

Big Blue boxes for DAQ, and PS crates: 2 already assembled and installed - need 2 more, will be assembled in January/Feb after OSU + Si at Cornell can spare the bits and pieces.

Power and cooling for Power supply boxes will be installed at the Si shutdown.

a) Low level VME C code for controlling the KU Boards, and hence the port cards.

b) Low level VME C code for running the Power Supply boards

c) Higher level C++ code that responds to CLEO run state changes and has (currently dummy) calls to the low level code above for both Power Supply crates and KU Crates.

1. Integrate the low level VME calls to the C++ code. (1 to 2 weeks of time - done by mid January)

b) Failure modes, interlocks and protection requirements. Richard Kass has volunteered to systematically evaluate all suggestions of possible failure modes. This is ongoing. Some specifics:

i) Develop the proper response to all possible error conditions.

We will begin cautiously, shutting down individual ladders completely, if a resetting of the appropriate voltages does not cure the observed problem. The 0th order version will be available before the end of January, and will continue to be refined thereafter.

c) Interface to the CLEO main Interlock system being built by Mike Ray/Georg. We expect the CLEO system to be more complete in January, and our interface to it will be ready at the end

of February.

The silicon power supply system consists of three major pieces of hardware crates, power supply boxes (PSB) and power supply cards (PSC) and associated software. Each item is discussed below.

Ia) Crate Overview

There are two power supply crates in the system. One resides on the east end the other the west end of the CLEO detector. A power supply crate is a standard CLEO3 VME crate with a special lower (J3) back-plane. This lower back-plane is used to distribute voltages (AVDD, AVDD, DVDD, Bias, etc.,11 in all) to the power supply cards that reside in the crate. At the back of each crate is a custom back panel to handle the many cables that are connected to the back of the crate (60 current carrying cables and 48 sense wires).

Ib) Crate Status

Both crates have been fabricated. One is in Ithaca, the other is at OSU . The crate at OSU is used to test Power Supply cards.

IIa) PSB overview

The entire silicon detector is run by 6 power supply boxes, 3 on the east side, 3 on the west. The boxes are organized as follows:

layers 1,2 east

layers 1,2 west

layer 3 east

layer 3 west

layer 4 east

layer 4 west

Each PSB contains a separate linear supply (9 total) for: AVDD,DVDD, AVDD2 (2), PC5, PC6

Bias+, Bias-, (+5V,+12V,-12V). Each power supply box can handle up to 28 hybrid/port-card/detectors.

Each PSB can be run in either local mode or remote (computer control) mode: In local mode voltages are turned on/off using 3 front panel switches. In remote mode a VME monitor board is used to digitize voltages and temperatures and set/trip relays to turn power supplies on/off. In this mode the monitor board can talk via an rs485 line to the slow control system. In both remote and local mode there is an interlock to insure that AVDD is on whenever AVDD2 is on.the PSB's are cooled using copper plates with H20 lines on top and bottom of each box. PSB's have been tested

at 120% layer 4 load (=26 hybrids at full power). Inside the PSB a rise in temperature of 20C with 0.4G/min H20 flowing in top & bottom cooling pipes was measured.

IIb) Power Supply Box Production Status

PSB production is well underway at OSU. Four boxes have been built. We expect to have six boxes completed (built and tested) by the end of December and all eight (6+2 spares) completed by mid-January. Each PSB has its own set of cables that connect the PSB to the crate.

These cables are fabricated at OSU.

In addition two prototype PSB's have been built. Each of these boxes contains the full compliment of individual power supplies but does not have the remote capabilities of the production supplies.

Thirty four power supply cards (17 per crate) are necessary to power the entire silicon detector.

The number of cards per layer is as follows:

5 PSC's layer 1,2 East

5 PSC's layer 1,2 West

5 PSC's layer 3 East

5 PSC's layer 3 West

7 PSC's layer 4 East

7 PSC's layer 4 West

Each power supply card (PSC) powers 4 portcards/4 hybrids/4 half-ladders. The card performs the following functions:

set bias voltages (nstrip, pstrip, pstop)

read voltages (avdd, bias, etc)

read currents (avdd, bias, etc)

read hybrid temperature

trip logic (V or I or T out of range)

The trip levels for voltage, current and hybrid temperature are all programmable. There are also diodes and fuses on the PSC to limit currents and voltage. In addition the PSC can send a signal directly to the PSB that will shut down the power supplies in the PSB.

The card has been extensively tested at OSU and at Wilson. The noise performance of the PSC/PSB system is quite good, approximately 1 ADC count (about 400e's).

Each card uses an ALTERA 10k30 as VME interface and state machine. There are also programmable XLINX chips on each board that control the voltage/current trip logic. Each card contains one 12 bit ADC which is used to digitize the voltages, currents and temperatures.

IIIb) Power Supply Card Production Schedule

Presently four working boards exist and we wish to build another 36. Ten boards were delivered to OSU last Saturday and the remaining 26 boards are expected to be delivered before Dec. 17.

A company to populate these boards has been chosen (the 4 working boards were populated at OSU) and they are currently populating 5 boards. We expect these boards to be at OSU either Dec 10 or 11th. Assuming these boards pass our quality control checks we will

have the company populate the rest of the boards. We would then expect to have all the populated boards sometime in the first week in January.

The software for the PSC consists of C routines to readout the board, code (AHDL) for the onboard ALTERA chip and code for the onboard XLINX chips (VHDL). The C routines exist and presently allow us to test and to operate the power supply system. We have working ALTERA and XILINX code that allows us to perform all the basic functions. We are developing more sophisticated code that checks voltages, currents and temperatures independently.

As with all projects the code is expected to evolve as we get more experience with the detector.

More information on the power supply system can be obtained from: http://www.lns.cornell.edu/~evt/PS_BOARD/psboard.html

Rationale: The L1/2 clamshells are mounted on the beam-pipe. The L1/2 ladders were re-tested after mounting and found to be in good shape

All of the L3 ladders have been tested after arrival at Cornell and were found to be in good working order. Therefore L3/4 was installed over layer 1/2 this week, and half of the silicon on Layer 3 has already been tested and found to be working well. It is therefore a realistic possibility that Si3 could be installed to complete CLEO III early in the New Year. The Si3 group is committed to do everything reasonably possible to achieve this goal. In the time before installation, the detector assembly on the beam-pipe must be completed, and the detector tested as fully as possible consistent with accepted practice and the installation schedule. The current level of effort and co-ordination must to be maintained by the entire Si3 team throughout this period, and the full support of LNS must also be maintained.

Between now and installation there are several phases:

(a)The time up until the shutdown date is known

(b)Preparation for installation

(c)Installation and subsequent testing

(d)Data taking, integration into CLEO III

The Si3 meeting Nov 13 was the beginning of the process of defining and reviewing what should happen in each of these periods, of developing and clarifying the schedule, establishing a responsibility matrix, reviewing the manpower involved and adding manpower where required.

The schedule implicitly sets a time frame for the delivery of components to LNS in order to implement the full tests required and to be ready for installation. Each sub-project is critically and continually examining their delivery schedule, the procedures and man-power for testing all components particularly those needed for the "full" test and subsequently for installation. Resources required from LNS such as space, technical help etc. have been, and are being, identified and requested. In addition steps have been taken to ensure that the lab space and test system are kept in operation at Newman. Also the wire-bonder at Newman has been restored to operation and has been guaranteed to be available for the sole use of Si3 during the whole assembly and testing period to allow for the completion of the remaining L4 ladders and subsequently for the repair of L4 ladders as needed.

Stabilize hybrids in clamshell plus more cable motion tests. Check new clamps. Second clamshell

out of box.. Layer 1 fully cabled. Jim Fast at LNS during this period. Layer 2 testing has to wait until installed on beam pipe. Preparation for installation of layer 1/2 on the beam pipe including:

(a) Beam-pipe prep: cooling line length, leak test beam-pipe cooling lines, leak test beam-pipe through roughing lines, mount sensor rings, dress cables for sensor rings.

(b) Fixture prep: test tip support, trim transition cone tips, stage transition cone, final modifications to East L1/2 temporary support, modify 2nd L1/2 temporary support, test and align L1/2 installation cart cut notch in construction beam

(c)L1/2 preparation:

Move L1/2 clamshell 1 and retest to check hybrid stability

Mount L1 cables

In clamshell 2 with appropriate clamp and cable modifications and hybrid reinforcements.

Cut L1/2 cooling lines to length.

Mount L1/2 clamshell 1 to L1/2 cart

Mount L1/2 clamshell 2 to L1/2 cart

Prepare cosmic ray test set-up..

Work on necessary infrastructure

Work on power supply boards.

Jeff reviewing and completing L1/2 installation prep and surveying.

Eckhard continues electrical testing. Verification of the Si3 performance benchmarks for individual ladders L1/2. Set-up cosmic ray test plus finish power supply software.

Delivery of L3/4 to Ithaca. Verification of the Si3 performance benchmarks for all individual L3 ladders and possibly accessible L4 ladders. Check sparsified readout. Jik Lee at LNS during this period.

Readout of Layer 0 in standalone mode.

L1/2 on beam pipe providing all fixtures are in place and all alignment has been done. Installation includes: staging L1/2, test closure, align and install upper L1/2 clamshell, install lower L1/2 clamshell and zip cones together, install L1/2 temporary supports. Transfer to L1/2 temporary supports, remove L1/2 cart. Survey final position..

Test of layer one and two on the beam pipe. Up to 8 hybrids at the same time using kluge boards at 1/8 power. Leak check L1/2 cooling lines.

Test all L1/2 ladders on the beam-pipe.

This period consists of mounting the L3/4 assembly on the beam-pipe. Ladders are inaccessible for part of this period.

Installation of L3/4 involves the following phases:

(a) Stage L3/4,

(b) Survey and align L3/4 to L/12.

(c) Install L3/4 over L1/2, and final adjustment of position of L3/4 relative to L1/2.

(d) Complete installation of transition cone 1.

(e) Dress L1/2 cable/cooling lines beam pipe cables etc on first side.

(f) Complete installation of transition cone 2.

(g) Dress cables and cooling lines on side 2.

(h) Partially cable L4 for cosmic ray testing

Prepare for comic ray tests over the Holiday period . A lexan cover for the detector and beam-pipe assembly has been fabricated. This will allow for a light-tight enclosure as well as a safe way to locate the upper scintillator of the cosmic ray telescope above the silicon.

Note added Dec 16:

During assembly of layer 1/2, eight inadvertent DC connections were introduced between the cone and the silicon, one is to the analog ground of a layer 2 hybrid, the remaining seven are to ground braids, also connected to analog ground. For the ground braids an easily implemented remedy is available, but this is not true for the hybrid. However, as long as this is the only hybrid shorted to this cone, and the cone remains electrically isolated, the noise performance of this part is expected to be good. In the silicon palace no increase in noise is seen.

Encouraged by the current health of Layer 1/2 and by the fact that layer 3 had been tested and found to be in good shape after arrival at Cornell, Layer 3/4 was installed around layer 1/2 this week. Half of the silicon on Layer 3 has already been tested and found to be working well. Testing is ongoing. It is possible that one layer 4 was damaged during installation, this has not yet been confirmed by an electrical test.

Rename the "crystal palace" the "silicon palace" at midnight on December 31^st.

Extended comic ray running of the assembled detector on the beam-pipe, including ladders from each layer, is planned. At this time 16 hybrids can be powered, either using 4PSC’s or a combination of PSC’s and the kluge board.. Either the L3/4 testing can be more extensive, or run in parallel with continued testing of L1/2 Re-benchmark silicon performance. This period also provides time for burn-in. Also a long term slow control test, aim for final boards, cables and software. Begin test of all situations slow control needs to respond to, from V,I,T monitoring to system failures.

Note added Dec 16: Si3 will review the status of the project during the first week of January, in light of the electrical testing information that is expected to be obtained during the Holiday period..

The three remaining layer 4 ladders will be installed during this period. The remaining L4 cables will be installed.

Mask support installation, which is roughly six days of work, will also occur during this period.

Mask support installation includes the following steps:

(a) Remove temporary support. Stage mask support 1 and route cables through mask

(b) Move mask support 1 to final position. Couple mask support 1 to silicon.

(c) Stage mask support 2 over beam pipe and route cables through mask

(d) Move mask support 2 to final position and install silicon supports

(e) Dress silicon and beam pipe cables and cooling lines

(f) Survey silicon

Note added Dec 16:

The committee requested that Si3 consider a "full crate test", with January 7^th as the suggested date to achieve this. This test would involve reading out multiple hybrids, where the port-cards are in a fully populated crescent crate that also includes a slow control buffer card and a Gaiderev card and the VME crates are fully populated with data boards and power supply cards, respectively. Unused power supply cards will power load boards.

Si3 believes that this is a good idea. However, the logistics and implementation details of this idea are still being discussed within the group. In order to avoid damage to the electronics, for example the VME crate controller, a fully populated VME crate requires significant cooling. The VME experts believe that fans will not provide adequate cooling, therefore full water cooling of the VME crates is required. The full crate test involves two VME crates, one for the data-boards, a second for the power supply cards. To do this test in the silicon palace we therefore need two completed "blue" boxes (these hold the crates and water cooling) and water for three power supply boxes (12 lines).. The infrastructure (plumbing) for the full crate test does not yet exist in the silicon palace.

While the infrastructure could certainly be installed, another possibility is to de-couple the full crate test from testing the silicon in the silicon palace. The final VME crates and cooling are located in the pit. Each crate would be filled with boards and long term stability studied. This would be independent of the testing ongoing in the silicon palace, where the electronics would be air-cooled.

The Si3 group has yet to determine which path it will follow. Eckhard has responsibility for making the final decision. However, by Jan 7th we do expect to have tested a full crescent crate with 1 Buffer card, 15 port cards connected to 15 hybrids and 1 Gaidarev card. The VME crates will be filled with as many data and power supply cards as are available. Both crates may be completely filled. The unused power supply cards will power load boards. Data boards that are not connected to a hybrid will perform a dummy readout. If not enough data or power supply cards are available, we will do a half crate test by Jan 7^th, and a full crate test by Jan 15th. Also, by Jan 7th the testing of most of the 122 hybrids will be done. It is possible that some Layer 4 cables may not be in place

until the end of this period and so the individual hybrids testing may not be completed until then.

As of today we have tested all hybrids in Layer 1,2 and half of the layer 3 hybrids after installation on the beam-pipe.

Section modified Dec 16:

A true full system test i.e. the entire system of 122 hybrids powered simultaneously, although not strictly necessary, would certainly be desirable at this point. We aim to approximate this with a 32 hybrid test. Cosmics will be taken with phi rotation (if possible). We will establish that benchmarks previously met by individual ladders are still met in 32 system. We will determine if there are new sources of noise that need to be fixed and can be fixed. We will demonstrate that the system is stable and can be calibrated. Final read out chain will be used. We have the option to repeat the 32 test sequentially for whole detector, but we will re-evaluate priorities once the installation date is known..

If a shutdown begins on Jan 30^th the silicon will not be needed in the IR until the CESR components have been removed. Testing of the silicon in the silicon palace will continue during this period.

Installation into CLEO/CESR is estimated to take 6-8 weeks, About 4-5 weeks after the start of the shutdown the installed silicon becomes available for testing while the IR is re-assembled. The full 122 hybrid system will be operated for the first time. Extensive cosmic ray testing is foreseen (hit, cluster and tracking: S/N , resolution, alignment and calibration) Utilize CLEO III trigger and DR information. At this stage slow control needs to able to respond to all system failures, run commands (RUN, FILL etc.) system configurations for various running states (HEP, calib) etc.

In addition to the silicon assembly work there are non-silicon tasks that need to be completed in preparation for a silicon installation shutdown. These include small modifications to existing installation carts, fabrication of additional support bars, a new and improved magic flange drive, pre-bending of cooling lines and crescent crate mounting brackets. Detailed final plans and schedules need to be prepared.

JJC has provided a sketch of the installation schedule. The duration of the installation is estimated at 6-8 weeks. This schedule could commence the week beginning Jan 31.

IR dis-assembly

Si3 and beam-pipe physical installation

VME DAQ, VME power and Power Supply crate installation

Beam-pipe utilities (cooling and roughing) extension to outside pole

Silicon cooling extension to outside pole

Silicon crescent crate installation and cables to crescent crate

Electronics crate population, utilities and testing

Silicon cables from crescent crate to electronics towers

Mask installation

Magic Flange installation

Alignment

Silicon testing

Pylon and orphan calorimeter re-installation.

REQ and REQ beam-pipe installation (magic flange operation)

Tisp (Ti sublimation pump) installation

Silicon testing

Pole-tip installation

End-cap calorimeter utility restoration

Q1 and Q2 physical installation

Silicon testing

Solenoid ramp

Q1-Q2 vacuum pipe installation

Q1 and Q2 utilities

Q1 and Q2 alignment

Clean-up

Problem resolution

Data taking commences

We have presented a plan to provide a fully operational silicon detector for CLEO. The schedule shown is compatible with a CESR shutdown of January 30th with the testing of the detector continuing until Feb 7^th during IR take apart.