CLEO Silicon III,10/15/99 9:34 AM -0500,PortCard, DataBoard,... update for t 1


To: CLEO Silicon III <si3list@mail.lns.cornell.edu>

From: George Brandenburg <gwb@lns.cornell.edu>

Subject: PortCard, DataBoard,... update for Today's meeting


Port Cards, CresCreates, DataBoards, Cables, Software, and all that...

GWB -- 10/15/99

PortCards: approx 140 fabricated, 130 tested OK, 20 at Cornell, rest at Harvard (a few spares needs repairs and retesting - AE & SH)

CresCrates: parts made for 8, 3 assembled and tested (assemble & test all 8 by Nov - AE)

DataBoards: 45 boards made, 35 stuffed, 5 in service, 2 of these NOK (bring more in service and make repairs soon - CRS & DK)

Hybrid Cable Sets: L1, 2, 3 all made & tested; L4 44 data and 18 power completed (all 52 L4 completed by Nov, then make spares - JOK)

PortCard Cable Sets: cable and connectors delivered for all, approx 8 done (finalize lengths, make tester, get Cornell tech for job by Nov - GWB)

LabVIEW Software: multiple hybrid version fo SVXDAQ in use (trivial to add TIM board triggering for calib running -GWB)

Crate CPU Load Constants Object: code outline & VME commands complete (need database format and commands, v1.0 by early Nov. - GWB & DK)

DSP Code: Draft version drains FIFOs successfully, dependent on Elliot (RICH) (finalize data tagging using database, v1.0 by early Nov? - DK) (later versions may have circular input buffer, data resparsification)


Printed for George Brandenburg <brandenburg@huhepl.harvard.edu>