Forward Pixel sensors

Task force

 

 

Chih Yung Chien, Hyosung Cho

John Hopkins University

Gino Bolla, Daniela Bortoletto, Carsten Rott, Amitava Roy

Purdue University

Simon Kwan

FNAL

 

 

 

 

 

 

 

Report for the Lehman Review

D. Bortoletto

 

Introduction

The CMS Forward Pixel Sensor Task Force has accomplished significant milestones during the past year. Here is a summary of our results that include:

  1. Continuing R&D with sensors fabricated at Brookhaven National Laboratory.
  2. Layout of a wafer for the first pixel sensor submission with vendors.
  3. Submission of our design to CSEM and Sintef.
  4. Development of an effective testing and evaluation plan of the prototype sensors
  5. Preliminary results on the prototype sensors

The engineering run with commercial vendors is a crucial step towards the choice of the substrate material, the evaluation of the processing and the optimization of the design of the pixel sensors. The sensor properties will be first studied through probing. The DC properties will be measured before and after proton, neutron and photon irradiations. Finally, the sensorís performance will be evaluated in beam tests that will take place at Fermilab and at CERN. This test program must be conducted very efficiently since the final production sensors must be ordered by the end of 2001.

Sensors design considerations

The operation of tracking detectors at the LHC will be challenging due to the radiation environment created by the expected luminosity of 1034cm-2s-1 and the 7 TeV beam energy. For the innermost tracking elements, such as the pixel detector, the radiation damage is dominated by the secondaries from the pp collisions. The estimates of the total fluence assume that full luminosity will be achieved only in the fourth year of LHC operation while the first 3 years will be equivalent to one year at full luminosity. In this scenario the CMS pixel layer at 4 cm is expected to reach 6 ´ 1014 hadrons/cm2 during the first 4 years of operation at the LHC.

The consequences of non-ionising energy loss in silicon are well known:

  1. Increase of the bulk leakage current leading to increased noise and power dissipation.
  2. Build-up of an effective p-doping, which requires ever increasing depletion voltages.
  3. Charge trapping in the depleted region.

After initial annealing a reverse annealing occurs where initially electrically inactive defects become active during several months after irradiation, thereby increasing the effective doping still more. This effect is temperature dependent and can be controlled by keeping the detectors at appropriate temperatures below 0° all the time once operation of LHC has started. This also helps in reducing the leakage currents.

In order to increase the useful operational lifetime of the silicon detectors running with partial depletion must be anticipated. This is more suitable for n-pixel readout, because after type inversion the depleted region will be on the pixel side.

 

Sensors R&D for Fpix

The Johns Hopkins group has lead an important program of detector R&D in collaboration with Brookhaven National Laboratory. The detectors are fabricated at BNL where it is possible to achieve faster prototype sensor production rate.

The R&D program has focused on the guard ring design. The multiguard ring is optimized not only to collect the dark current generated outside the active detector area but also control the E field distribution at the edge of the detector, provide a gradual and controlled potential drop and prevent avalanche breakdown.

In this design the guard ring on the n+ side are replaced by a single wide (640 m m) n+ implant as shown in the figure below. The n+ side and the edge of the p+ edge are always set at ground in operation to avoid even a small potential difference between the chip and the sensor's surface which could create an electric field higher than the breakdown field of air and cause damaging sparks.

Fig. 1 Multiguard ring design

 

 

 

 

 

 

 

The most recent sensors manufactured at BNL were produced using both standard and oxygen-enriched silicon substrates. The sensors were evaluated for radiation hardness up to a fluence of 1´ 1015 cm-2 both with (1 MeV equivalent) neutrons and 24 GeV/c protons. The DC characteristics of the sensors were measured before and after irradiation. The measurements performed on the devices allowed the determination of the depletion voltage, the leakage current and the distribution of the guard rings potential. The study confirms the results obtained by the Rose collaboration that oxygenated silicon irradiated to proton depletes at lower voltage than standard silicon. No improvement was found after neutron irradiation.

Measurement of the total leakage current (the sum of the guard and diode current) were used to determine the breakdown voltage at the guard. Measurements show no evidence for breakdown up to 600V after irradiation.

 

 

Fig. 2 Depletion voltage versus fluence

Engineering run submission

The design of a prototype wafer for Fpix was completed in May 1999 under the supervision of G. Bolla (Purdue University) and S. Kwan(Femilab). The request for bids from US-CMS was sent out to four companies: CSEM, Eurosys, CIS and Sintef. After evaluation of the response we submitted the design to Sintef and CSEM. Both submissions include structures for different CMS and BTeV in order to reduce the total cost.

The wafers have n+ pixels on n bulk silicon with p stop isolation. They include several sensors to match the prototype readout chip configurations that is under development at PSI (22´ 30, 26 ´ 40 and 52 ´ 53) and sensors which host 2 readout chips in order to investigate butting.

Fig. 3 Wafer layout

 

The wafers include structures to study the inter-pixel resistance and the inter-pixel capacitance. Pin diodes will allow the study of the breakdown of several multiguard configurations while MOS diodes will provide a measurement of the trapped charge in the oxide. The multiguard structures that we have implemented include designs developed at the John Hopkins University as well as a design that was developed at Padova University for the CMS microstrip sensors which had been already implemented by CSEM.

The sensors must conform the following specifications:

  1. 300 m m thick n-type silicon substrate
  2. Total thickness variation < 8 m m
  3. 1.0<r <2.0 kW · cm.
  4. breakdown voltage > 300 V
  5. leakage current < 50 nA/cm2
  6. Passivation on the p and n-side for mechanical protection
  7. Each company will provide at least 15 wafers, 3 of which will be oxygenated.
  8. The wafer will include test structures (PCMs) designed by the manufacturer to monitor the processing and the conformance to specifications.

The sensors manufactured by CSEM will use <111> orientation. This option was chosen because of stock availability. Other choices will have significantly delayed the delivery of the prototypes. CSEM will use oxygenated wafers following a process developed by the ROSE collaboration (1150 0C for 72 hours). CSEM will also provide under bump metallization (UBM) using a double layer of TiW/Au.

The sensors manufactured by Sintef will use <100> orientation and will be 270 m m thick. Sintef will not provided UBM. This option was chosen because of stock availability. Other choices will have significantly delayed the delivery of the prototypes.

The wafers will allow us to study several issues:

  1. The design of the multi guard ring structure for high voltage operation.
  2. Evaluation of a novel open ring p-stop concept that should allow biasing of the whole sensor through one bias pad.
  3. Evaluation of several substrate n-type silicon materials that are expected to be more radiation hard than the standard silicon.
  4. Effect of the crystal orientation (100 versus 111) of the n-type substrate material on the performance of the silicon sensors.
  5. Determination of the optimal sensor thickness.

The systematic studies of these issues will start as soon as the pixel sensors will be delivered. A beam test, planned for July 2000 at CERN will verify the performance of irradiated and non-irradiated prototype sensors with the chip.

Baseline Pixel sensor design

Si-sensors having n-pixels on an n-type substrate are chosen. On the n-side of the wafer, the charge collecting pixels are defined by n-implants surrounded by isolating p-stop rings. Fig. 1 shows the detailed mask layout. The width of the n-implants is foreseen to be about 80m m. The n-implants are covered by a standard metallisation, followed by a passivation layer with bump pad windows of » 13m m diameter. In each pair of pixel columns the bump pads are shifted by 25 m m to the outside, in order to fit the double column layout on the readout chip. This gives an alternating 100m m /200m m bump pad pattern. In the other direction the bump pad windows are shifted down in order to allow butting of the readout chips.

Around the n-implant of each pixel, two concentric p-stop rings are foreseen. Spacing and width of the floating rings is on the order of 8 m m and will be subject to further optimisation. The two p-stop rings should decrease the inter-pixel capacitance, that dominates the total pixel capacitance. The p-stop rings have both a small opening opposite each other. This creates a high resistive surface path between neighboring pixels of about 1.5-15 MW . A SPICE simulation by a Purdue undergraduate student has shown that an inter-pixel resistance below 100 MW keeps the n-implants for those pixels, where a bump bond connection to the readout amplifier has failed to form, at appropriate potential. This precaution should solve problems of stochastic discharges in non-connected pixels. Moreover it will allow testing of the overall leakage current of a complete pixel module before bump bonding. This resistive inter-pixel network has little effect on the fast signals.

Fig. 1 Layout of 150´ 150 m m pixel sensor. The double p-stop rings around each n-pixel are floating and allow a high resistive path to neighbors.

 

On the p-side of the wafer, a diode is implanted with appropriate metallisation, followed by a thick passivation (several m m). Special precautions will be taken for the guard rings on the p-side, where the whole potential drop between the bias voltage and the readout chips will occur. This is required since the edge of silicon must be at the potential of the n-side and especially of the readout chips to avoid dangerous sparks.

The need to operate the detectors at bias voltages up to ~300V influences the sensor design. Studies on p-type multiguard ring diodes have shown that the JHU guard ring design could achieve such specification.

Open p-stop design optimization

Several variation of the p-stop design have been implemented in the prototype wafer. For example a spiral p-stop is expected to yield a larger value of the inter pixel resistance. We have also implemented more traditional p-stop structures such as atoll and combined p-stops.

Fig. 6 Different open p-stop designs

 

 

 

Testing and evaluation plan.

The sensorís task force expects that FPix will order the final sensors by the end of 2001.

Since, the first prototype sensors arrived in March 2000 we must develop a very effective testing procedure which allow us to fully evaluate the sensors and still give us time for a pre-production submission.

We started this process by formulating a clear plan towards:

  1. Full evaluation of prototype sensors
  2. Production sensors quality control requirements
  3. Evaluating the readiness of the tests centers

 

Evaluation of prototype sensors

At this stage we must fully evaluate the design and the processing of the vendor. Each sensor and test structure on the wafer will be fully tested to check the quality of the process and the performance of the design. Irradiation tests must be conducted. This will required proton and neutron irradiation of two detectors up to 1, 3, 6 and 10 ´ 1014 particles/cm2.

The evaluation must verify:

  1. The guard ring design by measuring the leakage current as a function of the depletion voltage and by determining the breakdown voltage. The I-V curves must be done separately for the diode and the guard ring.
  2. Measure leakage current at the operation voltage
  3. Compare I-V curves for diodes and sensors to verify that there is no breakdown at the p-stops
  4. Biasing scheme through the open p-stop by measuring the IV at various locations on the pixel sensors. If the sensors can be fully biased then we should be able to obtain identical results.
  5. Determination of the depletion voltage. Before irradiation the depletion voltage will be determined through CV curves. After irradiation the depletion voltage will be measured by using TCT at JHU or signal collection with a pin diode laser at Purdue.
  6. Measure the interpixel capacitance as a function of the pitch for pixels sensors with pitch between 3 mm and 150 m m
  7. Measure the interpixel resistance of the channel between two pixel.

 

Sensors quality control

The set of quality control on the final sensors will depend strongly on the experience gained by measuring the prototypes. The detectors will be delivered already tested by the vendor. The vendor quality control will measure I-V on structures to verify the conformance to the electrical specifications. The test centers will:

  1. Register the detectors in a data base
  2. Perform optical inspection to cross check the quality and tag defects
  3. Full test with leakage current at fixed bias of a 5% of wafer to check for production stability

 

Readiness of the tests centers

We identified three locations with a well established record to carry out the testing program:

  1. Purdue University.
  1. Johns Hopkins University
  1. Fermilab

CV, IV and guard voltage measurements were performed at each location on diodes designed by JHU to define a set of standard procedures for the measurements. The comparison of the three setups was successful and the results showed good internal agreement.

 

Preliminary results on the prototype sensors

In March 2000 we have received 3 wafers from CSEM which were part of a submission between Purdue-PSI and Zurich. We also received 17 wafers from SINTEF as a result of our joint submission with BTeV.

CSEM

Figure 7 shows the structures on the CSEM wafer. The Purdue group has started to measure several diodes and pixel sensors on this wafer. The preliminary results from the measurements of the diodes show excellent performance:

1. Depletion voltage of » 150 V

2. Leakage current <40 nA/cm2

3. Breakdown voltage >1000 V

 

 

Figure 7: The Purdue-PSI-Zurich wafer. The structures with pink and white numbers are diodes and pixel sensors respectively.

 

The pixels sensors show similar leakage current/unit area and depletion voltage to the diodes but the breakdown voltage is significantly lower. We also found that sensors where each pixel has metallizion only on the bonding pad have a breakdown voltage of » 300V sensors where each pixels is completely metallized have a higher breakdown of about 500 V. Example of the different breakdown characteristics is shown in Fig. 9 and 10 respectively and summarized in Fig. 11. Further investigation of these results in taking place and it will require a fixture that allows double sided probing of the wafers and that it is currently under construction at Purdue University.

 

 

 

 

 

 

Figure 8

I-V curve for diode 9

Figure 9

I-V curve for Pixel 3

 

Figure 10

I-V curve for Pixel 22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 11: Breakdown voltage of pixel sensors.

 

 

 

Conclusions

Preliminary measurements of prototype sensors fabricated by a collaborative effort between JHU and BNL indicate that the guardring design implemented by Fpix operates above 600V without breakdown after irradiation. The first prototype sensors manufactured by a commercial vendor have become available in March 2000. The CMS sensors meet the design specifications. We have set a clear plan for an intense program of testing in 2000 that should allow Fpix to place the final order of the sensors by the end of 2001.