PST Event Triggers

Modeling the PST timing was fairly straight forward since that timingisdetermined by whenever 2 or more pixels in a 19 pixel PST patch fire incoincidence. The timing is thus set by the time of the second pixel. Thedisadvantage of this way of deriving the trigger time of the ADC gate isslewing for large summed logic pulses (ie. where a large number of pixels fire and contribute tothe analog sum of the logic pulses) and the resultant mismatch of the pixelsignal pulses and theposition of the ADC gate.To partially rectify this problem one can use an ADC gate large enough to accomodate any slewed pulse. This has the disadvantage of introducing extranoise into the pixel signal charge determination. The results of this study indicate that it is not necessary to do this. I mustadmit, however, that I have not looked at extremely big pulses. The 700 GeV proton shower used in this study had as it biggest pulses pixels with 100 PE's.

Another option (which is what we presently actually use) is to use the PST to determinethat we do have a trigger and to use a standard Multiplicity trigger using a CFDto obtain the timing. The modeling results indicate that this is the best option, though not by very much.

Below I give the parameters used to model the PST trigger time.

• PCFD ECL output pulse width: 18 ns, actual pulse is 12.4 ns wide with a tail out to 28.6 ns
• PST Threshold: 1.5 of logic pulse. i.e. 2 fold
• PST internal delay to strobe of patch bits to address register: 6 ns

This last item might actually provide cause for concern. There mightbe a problem which has to do with pixels, depending on their trigger times, being included inthe PST multiplicity decision but not in the pattern lookup. This would be dueto the delay in forming the address strobe to the lookup memory of the PST.However, due to thefact that the ECL pulses to the PST's are very long (> 18 ns), this does not appear to happen.